Volume 3B System Programming Guide_ Part 2 (794104), страница 97
Текст из файла (страница 97)
Beforesetting this bit, BIOS must executethe CPUID instruction withEAX = 0 and examine themaximum value returned inEAX[7:0].Vol. 3 B-47MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionIf the maximum value is greaterthan 3, then this bit is supported.Otherwise, this bit is notsupported and BIOS must not alterthe contents of this bit location.Setting this can cause unexpectedbehavior to software thatdepends on the availability ofCPUID leaves greater than 3.23SharedxTPR Message Disable.
(R/W)When set to 1, xTPR messages aredisabled. xTPR messages areoptional messages that allow theprocessor to inform the chipset ofits priority. The default isprocessor specific.24L1 Data Cache Context Mode.(R/W)When set, the L1 data cache isplaced in shared mode; when clear(default), the cache is placed inadaptive mode. This bit is onlyenabled for IA-32 processors thatsupport Intel Hyper-ThreadingTechnology.
See Section 10.5.6,“L1 Data Cache Context Mode.”When L1 is running in adaptivemode and CR3s are identical, datain L1 is shared across logicalprocessors. Otherwise, L1 is notshared and cache use iscompetitive.If the Context ID feature flag(ECX[10]) is set to 0 afterexecuting CPUID with EAX = 1, theability to switch modes is notsupported. BIOS must not alter thecontents ofIA32_MISC_ENABLE[24].B-48 Vol.
3MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique133:25Bit DescriptionReserved.34UniqueXD Bit Disable. (R/W)When set to 1, the Execute DisableBit feature (XD Bit) is disabled andthe XD Bit extended feature flagwill be clear (CPUID.80000001H:EDX[20]=0).When set to a 0 (default), theExecute Disable Bit feature (ifavailable) allows the OS to enablePAE paging and take advantage ofdata only pages.Assuming this bit is not set to 1and if CPUID.80000001H:EDX[20]=0, this feature is notsupported and BIOS must not alterthe contents of this bit location.Writing this bit to 1 when the XDBit extended feature flag is set to0 may generate a #GP exception.63:351A1H417MSR_PLATFORM_BRVReserved.3, 4, 6SharedPlatform Feature Requirements.(R)17:0Reserved.18PLATFORM Requirements.When set to 1, indicates theprocessor has specific platformrequirements.
The details of theplatform requirements are listed inthe respective data sheets of theprocessor.63:19Reserved.Vol. 3 B-49MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec1D7H471Register NameFields and FlagsModelAvailabilityShared/Unique1MSR_LER_FROM_LIP0, 1, 2,3, 4, 6UniqueBit DescriptionLast Exception Record FromLinear IP. (R)Contains a pointer to the lastbranch instruction that theprocessor executed prior to thelast exception that was generatedor the last interrupt that washandled.See Section 18.6.7, “LastException Records.”31:0From Linear IP.Linear address of the last branchinstruction.63:321D7H471Reserved.63:0UniqueFrom Linear IP.Linear address of the last branchinstruction (If IA-32e mode isactive).1D8H472MSR_LER_TO_LIP0, 1, 2,3, 4, 6UniqueLast Exception Record To LinearIP.
(R)This area contains a pointer to thetarget of the last branchinstruction that the processorexecuted prior to the lastexception that was generated orthe last interrupt that washandled.See Section 18.6.7, “LastException Records.”31:0From Linear IP.Linear address of the target of thelast branch instruction.63:32B-50 Vol.
3Reserved.MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec1D8H472Register NameFields and FlagsModelAvailability63:0Shared/Unique1UniqueBit DescriptionFrom Linear IP.Linear address of the target of thelast branch instruction (If IA-32emode is active).1D9H473MSR_DEBUGCTLA0, 1, 2,3, 4, 6UniqueDebug Control. (R/W)Controls how several debugfeatures are used. Bit definitionsare discussed in the referencedsection.See Section 18.6.2,“MSR_DEBUGCTLA MSR.”1DAH474MSR_LASTBRANCH_TOS0, 1, 2,3, 4, 6UniqueLast Branch Record Stack TOS.(R)Contains an index (0-3 or 0-15)that points to the top of the lastbranch record stack (that is, thatpoints the index of the MSRcontaining the most recent branchrecord).See Section 18.6.3, “LBR Stack”;and addresses 1DBH-1DEH and680H-68FH.1DBH475MSR_LASTBRANCH_00, 1, 2UniqueLast Branch Record 0.
(R/W)One of four last branch recordregisters on the last branch recordstack. It contains pointers to thesource and destination instructionfor one of the last four branches,exceptions, or interrupts that theprocessor took.MSR_LASTBRANCH_0 throughMSR_LASTBRANCH_3 at 1DBH1DEH are available only on family0FH, models 0H-02H. They havebeen replaced by the MSRs at680H-68FH and 6C0H-6CFH.Vol. 3 B-51MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexRegister NameFields and FlagsDecModelAvailabilityShared/Unique1Bit DescriptionSee Section 18.6, “Last Branch,Interrupt, and Exception Recording(Processors based on IntelNetBurst® Microarchitecture).”1DDH477MSR_LASTBRANCH_20, 1, 2UniqueLast Branch Record 2.See description of theMSR_LASTBRANCH_0 MSR at1DBH.1DEH478MSR_LASTBRANCH_30, 1, 2UniqueLast Branch Record 3.See description of theMSR_LASTBRANCH_0 MSR at1DBH.200H201H202H203H204H205H206HB-52 Vol.
3512513514515516517518IA32_MTRR_PHYSBASE00, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK00, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE10, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK10, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE20, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK20, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE30, 1, 2,3, 4, 6SharedVariable Range Base MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs”.Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec207H519208H209H20AH20BH20CH20DH20EH20FH250H258H520521522523524525526527592600Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_MTRR_PHYSMASK30, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE40, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK40, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE50, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK50, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE60, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK60, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSBASE70, 1, 2,3, 4, 6SharedIA32_MTRR_PHYSMASK70, 1, 2,3, 4, 6SharedIA32_MTRR_FIX64K_000000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX16K_800000, 1, 2,3, 4, 6SharedBit DescriptionVariable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Variable Range Mask MTRR.See Section 10.11.2.3, “VariableRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Vol.
3 B-53MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec259H601268H269H26AH26BH26CH26DH26EH26FH277HB-54 Vol. 3616617618619620621622623631Register NameFields and FlagsModelAvailabilityShared/Unique1IA32_MTRR_FIX16K_A00000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_C00000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_C80000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_D00000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_D80000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_E00000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_E80000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_F00000, 1, 2,3, 4, 6SharedIA32_MTRR_FIX4K_F80000, 1, 2,3, 4, 6SharedIA32_CR_PAT0, 1, 2,3, 4, 6UniqueBit DescriptionFixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs”.Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs”.Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Fixed Range MTRR.See Section 10.11.2.2, “FixedRange MTRRs.”Page Attribute Table.See Section 10.11.2.2, “FixedRange MTRRs.”MODEL-SPECIFIC REGISTERS (MSRS)Table B-2.
MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressHexDec2FFH767Register NameFields and FlagsIA32_MTRR_DEF_TYPEModelAvailabilityShared/Unique10, 1, 2,3, 4, 6SharedBit DescriptionDefault Memory Types. (R/W)Sets the memory type for theregions of physical memory thatare not mapped by the MTRRs.See Section 10.11.2.1,“IA32_MTRR_DEF_TYPE MSR.”300H768MSR_BPU_COUNTER00, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”301H769MSR_BPU_COUNTER10, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”302H770MSR_BPU_COUNTER20, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”303H771MSR_BPU_COUNTER30, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”304H772MSR_MS_COUNTER00, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”305H773MSR_MS_COUNTER10, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”306H774MSR_MS_COUNTER20, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”307H775MSR_MS_COUNTER30, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”308H776MSR_FLAME_COUNTER00, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”309H777MSR_FLAME_COUNTER10, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”30AH778MSR_FLAME_COUNTER20, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”30BH779MSR_FLAME_COUNTER30, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”3OCH780MSR_IQ_COUNTER00, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”3ODH781MSR_IQ_COUNTER10, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”Vol.
3 B-55MODEL-SPECIFIC REGISTERS (MSRS)Table B-2. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.)RegisterAddressRegister NameFields and FlagsModelAvailabilityShared/Unique1Bit DescriptionHexDec3OEH782MSR_IQ_COUNTER20, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”3OFH783MSR_IQ_COUNTER30, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”310H784MSR_IQ_COUNTER40, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”311H785MSR_IQ_COUNTER50, 1, 2,3, 4, 6SharedSee Section 18.15.2,“Performance Counters.”360H864MSR_BPU_CCCR00, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”361H865MSR_BPU_CCCR10, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”362H866MSR_BPU_CCCR20, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”363H867MSR_BPU_CCCR30, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”364H868MSR_MS_CCCR00, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”365H869MSR_MS_CCCR10, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”366H870MSR_MS_CCCR20, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”367H871MSR_MS_CCCR30, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”368H872MSR_FLAME_CCCR00, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”369H873MSR_FLAME_CCCR10, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”36AH874MSR_FLAME_CCCR20, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”36BH875MSR_FLAME_CCCR30, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”36CH876MSR_IQ_CCCR00, 1, 2,3, 4, 6SharedSee Section 18.15.3, “CCCR MSRs.”B-56 Vol.
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