Volume 2B Instruction Set Reference N-Z (794102)
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Intel® 64 and IA-32 ArchitecturesSoftware Developer’s ManualVolume 2B:Instruction Set Reference, N-ZNOTE: The Intel 64 and IA-32 Architectures Software Developer's Manualconsists of five volumes: Basic Architecture, Order Number 253665;Instruction Set Reference A-M, Order Number 253666; Instruction SetReference N-Z, Order Number 253667; System Programming Guide,Part 1, Order Number 253668; System Programming Guide, Part 2,Order Number 253669. Refer to all five volumes when evaluating yourdesign needs.Order Number: 253667-023USMay 2007INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts orincompatibilities arising from their unauthorized use.The Intel® 64 architecture processors may contain design defects or errors known as errata. Current characterized errata are available on request.Hyper-Threading Technology requires a computer system with an Intel® processor supporting HyperThreading Technology and an HT Technology enabled chipset, BIOS and operating system.
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Consult with your system vendor for more information.Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capabilityand a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placingyour product order.Copies of documents which have an ordering number and are referenced in this document, or other Intelliterature, may be obtained from:Intel CorporationP.O.
Box 5937Denver, CO 80217-9808or call 1-800-548-4725or visit Intel’s website at http://www.intel.comCopyright © 1997-2007 Intel Corporationii Vol. 2BCHAPTER 4INSTRUCTION SET REFERENCE, N-Z4.1INSTRUCTIONS (N-Z)Chapter 4 continues an alphabetical discussion of Intel® 64 and IA-32 instructions(N-Z). See also: Chapter 3, “Instruction Set Reference, A-M,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 2A.Vol. 2B 4-1INSTRUCTION SET REFERENCE, N-ZNEG—Two's Complement NegationOpcodeInstruction64-Bit Mode Compat/Leg ModeDescriptionF6 /3NEG r/m8ValidValidTwo's complement negate r/m8.REX + F6 /3NEG r/m8*ValidN.E.Two's complement negate r/m8.F7 /3NEG r/m16ValidValidTwo's complement negater/m16.F7 /3NEG r/m32ValidValidTwo's complement negater/m32.REX.W + F7 /3NEG r/m64ValidN.E.Two's complement negater/m64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.DescriptionReplaces the value of operand (the destination operand) with its two's complement.(This operation is equivalent to subtracting the operand from 0.) The destinationoperand is located in a general-purpose register or a memory location.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationIF DEST = 0THEN CF ← 0;ELSE CF ← 1;FI;DEST ← [– (DEST)]Flags AffectedThe CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF,AF, and PF flags are set according to the result.4-2 Vol.
2BNEG—Two's Complement NegationINSTRUCTION SET REFERENCE, N-ZProtected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.NEG—Two's Complement NegationVol.
2B 4-3INSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.4-4 Vol. 2BNEG—Two's Complement NegationINSTRUCTION SET REFERENCE, N-ZNOP—No OperationOpcodeInstruction64-Bit Mode Compat/Leg ModeDescription90NOPValidValidOne byte no-operation instruction.0F 1F /0NOP r/m16ValidValidMulti-byte no-operation instruction.0F 1F /0NOP r/m32ValidValidMulti-byte no-operation instruction.DescriptionThis instruction performs no operation.
It is a one-byte or multi-byte NOP that takesup space in the instruction stream but does not impact machine context, except forthe EIP register.The multi-byte form of NOP is available on processors with model encoding:•CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111BThe multi-byte NOP instruction does not alter the content of a register and will notissue a memory operation. The instruction’s operation is the same in non-64-bitmodes and 64-bit mode.OperationThe one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AXinstruction.The multi-byte NOP instruction performs no operation on supported processors andgenerates undefined opcode exception on processors that do not support the multibyte NOP instruction.The memory operand form of the instruction allows software to create a bytesequence of “no operation” as one instruction.
For situations where multiple-byteNOPs are needed, the recommended operations (32-bit mode and 64-bit mode) are:Table 4-1. Recommended Multi-Byte Sequence of NOP InstructionLengthAssemblyByte Sequence2 bytes66 NOP66 90H3 bytesNOP DWORD ptr [EAX]0F 1F 00H4 bytesNOP DWORD ptr [EAX + 00H]0F 1F 40 00H5 bytesNOP DWORD ptr [EAX + EAX*1 + 00H]0F 1F 44 00 00H6 bytes66 NOP DWORD ptr [EAX + EAX*1 + 00H]66 0F 1F 44 00 00H7 bytesNOP DWORD ptr [EAX + 00000000H]0F 1F 80 00 00 00 00HNOP—No OperationVol. 2B 4-5INSTRUCTION SET REFERENCE, N-ZTable 4-1.
Recommended Multi-Byte Sequence of NOP Instruction (Contd.)LengthAssemblyByte Sequence8 bytesNOP DWORD ptr [EAX + EAX*1 + 00000000H]0F 1F 84 00 00 00 00 00H9 bytes66 NOP DWORD ptr [EAX + EAX*1 +00000000H]66 0F 1F 84 00 00 00 0000HFlags AffectedNone.Exceptions (All Operating Modes)#UD4-6 Vol. 2BIf the LOCK prefix is used.NOP—No OperationINSTRUCTION SET REFERENCE, N-ZNOT—One's Complement NegationOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionF6 /2NOT r/m8ValidValidReverse each bit of r/m8.REX + F6 /2NOT r/m8*ValidN.E.Reverse each bit of r/m8.F7 /2NOT r/m16ValidValidReverse each bit of r/m16.F7 /2NOT r/m32ValidValidReverse each bit of r/m32.REX.W + F7 /2NOT r/m64ValidN.E.Reverse each bit of r/m64.NOTES:* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.DescriptionPerforms a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on thedestination operand and stores the result in the destination operand location.
Thedestination operand can be a register or a memory location.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15).
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