Volume 2A Instruction Set Reference A-M (794101)
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Intel® 64 and IA-32 ArchitecturesSoftware Developer’s ManualVolume 2A:Instruction Set Reference, A-MNOTE: The Intel 64 and IA-32 Architectures Software Developer's Manualconsists of five volumes: Basic Architecture, Order Number 253665;Instruction Set Reference A-M, Order Number 253666; Instruction SetReference N-Z, Order Number 253667; System Programming Guide,Part 1, Order Number 253668; System Programming Guide, Part 2,Order Number 253669. Refer to all five volumes when evaluating yourdesign needs.Order Number: 253666-034USMarch 2010INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCHPRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIEDWARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIESRELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANYPATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.Intel may make changes to specifications and product descriptions at any time, without notice.
Designersmust not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts orincompatibilities arising from future changes to them. The information here is subject to change without notice.
Do not finalize a design with this information.The Intel® 64 architecture processors may contain design defects or errors known as errata. Current characterized errata are available on request.Intel® Hyper-Threading Technology requires a computer system with an Intel® processor supporting HyperThreading Technology and an Intel® HT Technology enabled chipset, BIOS and operating system.Performance will vary depending on the specific hardware and software you use.
For more information, seehttp://www.intel.com/technology/hyperthread/index.htm; including details on which processors support Intel HTTechnology.Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtualmachine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations. Intel® VirtualizationTechnology-enabled BIOS and VMM applications are currently in development.64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture.
Processors will not operate(including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capabilityand a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo,Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, Intel Atom, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placingyour product order.Copies of documents which have an ordering number and are referenced in this document, or other Intelliterature, may be obtained by calling 1-800-548-4725, or by visiting Intel’s website at http://www.intel.comCopyright © 1997-2010 Intel Corporationii Vol.
2ACONTENTSPAGECHAPTER 1ABOUT THIS MANUAL1.1IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . .1.3NOTATIONAL CONVENTIONS . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3.1Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . .1.3.2Reserved Bits and Software Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3.3Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .1.3.4Hexadecimal and Binary Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3.5Segmented Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . .1.3.6Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.3.7A New Syntax for CPUID, CR, and MSR Values . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-11-31-41-41-51-61-61-61-71-71-8CHAPTER 2INSTRUCTION FORMAT2.1INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, ANDVIRTUAL-8086 MODE 2-12.1.1Instruction Prefixes . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.1.2Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.1.3ModR/M and SIB Bytes . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.1.4Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.1.5Addressing-Mode Encoding of ModR/M and SIB Bytes . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 2-42.2IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92.2.1REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92.2.1.1Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102.2.1.2More on REX Prefix Fields . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102.2.1.3Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132.2.1.4Direct Memory-Offset MOVs. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 2-132.2.1.5Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142.2.1.6RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142.2.1.7Default 64-Bit Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-152.2.2Additional Encodings for Control and Debug Registers . . . . .
. . . . . . . . . . . . . . . . . . . . . . 2-15CHAPTER 3INSTRUCTION SET REFERENCE, A-M3.1INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.1Instruction Format . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.1.1Opcode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.1.2Instruction Column in the Opcode Summary Table .
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