Volume 3A System Programming Guide_ Part 1 (794103)
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Intel® 64 and IA-32 ArchitecturesSoftware Developer’s ManualVolume 3A:System Programming Guide, Part 1NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manualconsists of five volumes: Basic Architecture, Order Number 253665;Instruction Set Reference A-M, Order Number 253666; Instruction SetReference N-Z, Order Number 253667; System Programming Guide,Part 1, Order Number 253668; System Programming Guide, Part 2, OrderNumber 253669. Refer to all five volumes when evaluating your designneeds.Order Number: 253668-023USMay 2007Information in this document is provided in connection with Intel products. No license, express or implied,by estoppel or otherwise, to any intellectual property rights is granted by this document.
Except as providedin Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Inteldisclaims any express or implied warranty, relating to sale and/or use of Intel products including liability orwarranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, orlife sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Developers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Improper use of reserved or undefined features or instructions may cause unpredictable behavior or failure in developer's software code when running on an Intel processor.
Intel reservesthese features or instructions for future definition and shall have no responsibility whatsoever for conflictsor incompatibilities arising from their unauthorized use.The Intel® 64 architecture processors may contain design defects or errors known as errata. Current characterized errata are available on request.Hyper-Threading Technology requires a computer system with an Intel® processor supporting HyperThreading Technology and an HT Technology enabled chipset, BIOS and operating system.
Performance willvary depending on the specific hardware and software you use. For more information, see http://www.intel.com/technology/hyperthread/index.htm; including details on which processors support HT Technology.Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtualmachine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations.
Intel® VirtualizationTechnology-enabled BIOS and VMM applications are currently in development.64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Processors will not operate(including 32-bit operation) without an Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capabilityand a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.*Other names and brands may be claimed as the property of others.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placingyour product order.Copies of documents which have an ordering number and are referenced in this document, or other Intelliterature, may be obtained from:Intel CorporationP.O.
Box 5937Denver, CO 80217-9808or call 1-800-548-4725or visit Intel’s website at http://www.intel.comCopyright © 1997-2007 Intel Corporationii Vol. 3ACONTENTSPAGECHAPTER 1ABOUT THIS MANUAL1.11.21.31.3.11.3.21.3.31.3.41.3.51.3.61.3.71.4PROCESSORS COVERED IN THIS MANUAL . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6Reserved Bits and Software Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 1-6Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7Hexadecimal and Binary Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Segmented Addressing. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Exceptions . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10CHAPTER 2SYSTEM ARCHITECTURE OVERVIEW2.12.1.12.1.1.12.1.22.1.2.12.1.32.1.3.12.1.42.1.4.12.1.52.1.5.12.1.62.1.6.12.1.72.22.32.3.12.42.4.12.4.22.4.32.4.42.52.5.12.62.6.12.6.22.6.32.6.42.6.52.6.6OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2Global and Local Descriptor Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5Global and Local Descriptor Tables in IA-32e Mode . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 2-5System Segments, Segment Descriptors, and Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5Gates in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 2-6Task-State Segments and Task Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6Task-State Segments in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 2-7Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7Interrupt and Exception Handling IA-32e Mode . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 2-7Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8Memory Management in IA-32e Mode . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . 2-8System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9System Registers in IA-32e Mode . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 2-9Other System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12System Flags and Fields in IA-32e Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 2-15MEMORY-MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15Global Descriptor Table Register (GDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16Local Descriptor Table Register (LDTR) . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16IDTR Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17Task Register (TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17CPUID Qualification of Control Register Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25SYSTEM INSTRUCTION SUMMARY. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25Loading and Storing System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27Verifying of Access Privileges . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28Loading and Storing Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29Invalidating Caches and TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 2-29Controlling the Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29Reading Performance-Monitoring and Time-Stamp Counters . . . . . . . . . . . . . . . . . . . . . 2-30Vol. 3A iiiCONTENTSPAGE2.6.6.12.6.72.6.7.1Reading Counters in 64-Bit Mode . . .
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