Volume 3A System Programming Guide_ Part 1 (794103), страница 103
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SeeFigure 10-1. Cache availability is described below:•Intel Core 2 processor and Intel Xeon processor 5100 Series— The L1cache is divided into two sections: one section is dedicated to caching instructions (pre-decoded instructions) and the other caches data. The L2 cache is aunified data and instruction cache is located on the processor chip; it is sharedVol. 3 10-3MEMORY CACHE CONTROLbetween two processor cores in a dual-core processor implementation.
No tracecache is implemented.•Intel Core Solo and Intel Core Duo processors — The L1 cache is divided intotwo sections: one section is dedicated to caching instructions (pre-decodedinstructions) and the other caches data. The L2 cache is a unified data andinstruction cache located on the processor chip.
It is shared between twoprocessor cores in a dual-core processor implementation. No trace cache isimplemented.•Pentium 4 and Intel Xeon processors — The trace cache caches decodedinstructions (μops) from the instruction decoder and the L1 cache contains data.The L2 and L3 caches are unified data and instruction caches located on theprocessor chip. Note that the L3 cache is only implemented on some Intel Xeonprocessors.•P6 family processors — The L1 cache is divided into two sections: onededicated to caching instructions (pre-decoded instructions) and the other tocaching data. The L2 cache is a unified data and instruction cache located on theprocessor chip. P6 family processors do not implement a trace cache.•Pentium processors — The L1 cache has the same structure as on P6 familyprocessors.
There is no trace cache. The L2 cache is a unified data and instructioncache external to the processor chip on earlier Pentium processors andimplemented on the processor chip in later Pentium processors. For Pentiumprocessors where the L2 cache is external to the processor, access to the cache isthrough the system bus.For processors based on Intel Core and Intel NetBurst microarchitectures, Intel CoreDuo, Intel Core Solo and Pentium M processors, the cache lines for the L1 and L2caches (and L3 caches if supported) are 64 bytes wide. The processor always reads acache line from system memory beginning on a 64-byte boundary. (A 64-bytealigned cache line begins at an address with its 6 least-significant bits clear.) A cacheline can be filled from memory with a 8-transfer burst transaction.
The caches do notsupport partially-filled cache lines, so caching even a single doubleword requirescaching an entire line.The L1 and L2 cache lines in the P6 family and Pentium processors are 32 bytes wide,with cache line reads from system memory beginning on a 32-byte boundary (5least-significant bits of a memory address clear.) A cache line can be filled frommemory with a 4-transfer burst transaction. Partially-filled cache lines are notsupported.The trace cache in processors based on Intel NetBurst microarchitecture is availablein all execution modes: protected mode, system management mode (SMM), andreal-address mode.
The L1,L2, and L3 caches are also available in all executionmodes; however, use of them must be handled carefully in SMM (see Section 24.4.2,“SMRAM Caching”).The TLBs store the most recently used page-directory and page-table entries. Theyspeed up memory accesses when paging is enabled by reducing the number ofmemory accesses that are required to read the page tables stored in system10-4 Vol. 3MEMORY CACHE CONTROLmemory. The TLBs are divided into four groups: instruction TLBs for 4-KByte pages,data TLBs for 4-KByte pages; instruction TLBs for large pages (2-MByte or 4-MBytepages), and data TLBs for large pages. The TLBs are normally active only in protectedmode with paging enabled. When paging is disabled or the processor is in realaddress mode, the TLBs maintain their contents until explicitly or implicitly flushed(see Section 10.9, “Invalidating the Translation Lookaside Buffers (TLBs)”).The store buffer is associated with the processors instruction execution units.
Itallows writes to system memory and/or the internal caches to be saved and in somecases combined to optimize the processor’s bus accesses. The store buffer is alwaysenabled in all execution modes.The processor’s caches are for the most part transparent to software. When enabled,instructions and data flow through these caches without the need for explicit software control.
However, knowledge of the behavior of these caches may be useful inoptimizing software performance. For example, knowledge of cache dimensions andreplacement algorithms gives an indication of how large of a data structure can beoperated on at once without causing cache thrashing.In multiprocessor systems, maintenance of cache consistency may, in rare circumstances, require intervention by system software. For these rare cases, the processorprovides privileged cache control instructions for use in flushing caches and forcingmemory ordering.The Pentium III, Pentium 4, and Intel Xeon processors introduced several instructionsthat software can use to improve the performance of the L1, L2, and L3 caches,including the PREFETCHh and CLFLUSH instructions and the non-temporal moveinstructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and MOVNTPD).
The use ofthese instructions are discussed in Section 10.5.5, “Cache Management Instructions.”10.2CACHING TERMINOLOGYIA-32 processors (beginning with the Pentium processor) and Intel 64 processors usethe MESI (modified, exclusive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in other processors (see Section 10.4, “CacheControl Protocol”).When the processor recognizes that an operand being read from memory is cacheable, the processor reads an entire cache line into the appropriate cache (L1, L2, L3,or all). This operation is called a cache line fill.
If the memory location containingthat operand is still cached the next time the processor attempts to access theoperand, the processor can read the operand from the cache instead of going back tomemory. This operation is called a cache hit.When the processor attempts to write an operand to a cacheable area of memory, itfirst checks if a cache line for that memory location exists in the cache.
If a validcache line does exist, the processor (depending on the write policy currently in force)can write the operand into the cache instead of writing it out to system memory. ThisVol. 3 10-5MEMORY CACHE CONTROLoperation is called a write hit. If a write misses the cache (that is, a valid cache lineis not present for area of memory being written to), the processor performs a cacheline fill, write allocation. Then it writes the operand into the cache line and(depending on the write policy currently in force) can also write it out to memory. Ifthe operand is to be written out to memory, it is written first into the store buffer, andthen written from the store buffer to memory when the system bus is available.(Note that for the Pentium processor, write misses do not result in a cache line fill;they always result in a write to memory.
For this processor, only read misses result incache line fills.)When operating in an MP system, IA-32 processors (beginning with the Intel486processor) and Intel 64 processors have the ability to snoop other processor’saccesses to system memory and to their internal caches. They use this snoopingability to keep their internal caches consistent both with system memory and withthe caches in other processors on the bus.
For example, in the Pentium and P6 familyprocessors, if through snooping one processor detects that another processorintends to write to a memory location that it currently has cached in shared state,the snooping processor will invalidate its cache line forcing it to perform a cache linefill the next time it accesses the same memory location.Beginning with the P6 family processors, if a processor detects (through snooping)that another processor is trying to access a memory location that it has modified inits cache, but has not yet written back to system memory, the snooping processorwill signal the other processor (by means of the HITM# signal) that the cache line isheld in modified state and will preform an implicit write-back of the modified data.The implicit write-back is transferred directly to the initial requesting processor andsnooped by the memory controller to assure that system memory has been updated.Here, the processor with the valid data may pass the data to the other processorswithout actually writing it to system memory; however, it is the responsibility of thememory controller to snoop this operation and update memory.10.3METHODS OF CACHING AVAILABLEThe processor allows any area of system memory to be cached in the L1, L2, and L3caches.
In individual pages or regions of system memory, it allows the type ofcaching (also called memory type) to be specified (see Section 10.5). Memory typescurrently defined for the Intel 64 and IA-32 architectures are (see Table 10-2):•Strong Uncacheable (UC) —System memory locations are not cached.
Allreads and writes appear on the system bus and are executed in program orderwithout reordering. No speculative memory accesses, page-table walks, orprefetches of speculated branch targets are made. This type of cache-control isuseful for memory-mapped I/O devices. When used with<b>Текст обрезан, так как является слишком большим</b>.
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