Volume 3A System Programming Guide_ Part 1 (794103), страница 100
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This storage unit consists of oneor more update blocks. An update block is a contiguous 2048-byte block of memory.The BIOS for a single processor system need only provide update blocks to store onemicrocode update. If the BIOS for a multiple processor system is intended to supportmixed processor steppings, then the BIOS needs to provide enough update blocks tostore each unique microcode update or for each processor socket on the OEM’ssystem board.The BIOS is responsible for managing the NVRAM update blocks.
This includesgarbage collection, such as removing microcode updates that exist in NVRAM forwhich a corresponding processor does not exist in the system. This specification onlyprovides the mechanism for ensuring security, the uniqueness of an entry, and thatstale entries are not loaded. The actual update block management is implementationspecific on a per-BIOS basis.As an example, the BIOS may use update blocks sequentially in ascending order withCPU signatures sorted versus the first available block.
In addition, garbage collectionmay be implemented as a setup option to clear all NVRAM slots or as BIOS code thatsearches and eliminates unused entries during boot.NOTESFor IA-32 processors starting with family 0FH and model 03H andIntel 64 processors, the microcode update may be as large as 16KBytes. Thus, BIOS must allocate 8 update blocks for each microcodeupdate. In a MP system, a common microcode update may besufficient for each socket in the system.For IA-32 processors earlier than family 0FH and model 03H, themicrocode update is 2 KBytes.
An MP-capable BIOS that supportsmultiple steppings must allocate a block for each socket in the system.A single-processor BIOS that supports variable-sized microcodeupdate and fixed-sized microcode update must allocate one 16-KByteregion and a second region of at least 2 KBytes.The following algorithm (Example 9-11) describes the steps performed during BIOSinitialization used to load the updates into the processor(s). The algorithm assumes:•The BIOS ensures that no update contained within NVRAM has a header versionor loader version that does not match one currently supported by the BIOS.•••The update contains a correct checksum.The BIOS ensures that (at most) one update exists for each processor stepping.Older update revisions are not allowed to overwrite more recent ones.9-50 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATIONThese requirements are checked by the BIOS during the execution of the writeupdate function of this interface. The BIOS sequentially scans through all of theupdate blocks in NVRAM starting with index 0. The BIOS scans until it finds an updatewhere the processor fields in the header match the processor signature (extendedfamily, extended model, type, family, model, and stepping) as well as the platformbits of the current processor.Example 9-11.
Pseudo Code, Checks Required Prior to Loading an UpdateFor each processor in the system{Determine the Processor Signature via CPUID function 1;Determine the Platform Bits ← 1 << IA32_PLATFORM_ID[52:50];For (I ← UpdateBlock 0, I < NumOfBlocks; I++){If (Update.Header_Version == 0x00000001){If ((Update.ProcessorSignature == Processor Signature) &&(Update.ProcessorFlags & Platform Bits)){Load Update.UpdateData into the Processor;Verify update was correctly loaded into the processorGo on to next processorBreak;}Else If (Update.TotalSize > (Update.DataSize + 48)){N ← 0While (N < Update.ExtendedSignatureCount){If ((Update.ProcessorSignature[N] ==Processor Signature) &&(Update.ProcessorFlags[N] & Platform Bits)){Load Update.UpdateData into the Processor;Verify update correctly loaded into the processorGo on to next processorBreak;}N ← N + 1}I ← I + (Update.TotalSize / 2048)If ((Update.TotalSize MOD 2048) == 0)I ← I + 1}}Vol.
3 9-51PROCESSOR MANAGEMENT AND INITIALIZATION}}NOTESThe platform Id bits in IA32_PLATFORM_ID are encoded as a threebit binary coded decimal field. The platform bits in the microcodeupdate header are individually bit encoded. The algorithm must do atranslation from one format to the other prior to doing a check.When performing the INT 15H, 0D042H functions, the BIOS must assume that thecaller has no knowledge of platform specific requirements.
It is the responsibility ofBIOS calls to manage all chipset and platform specific prerequisites for managing theNVRAM device. When writing the update data using the Write Update sub-function,the BIOS must maintain implementation specific data requirements (such as theupdate of NVRAM checksum). The BIOS should also attempt to verify the success ofwrite operations on the storage device used to record the update.9.11.8.2Responsibilities of the Calling ProgramThis section of the document lists the responsibilities of a calling program using theinterface specifications to load microcode update(s) into BIOS NVRAM.•The calling program should call the INT 15H, 0D042H functions from a pure realmode program and should be executing on a system that is running in pure realmode.•The caller should issue the presence test function (sub function 0) and verify thesignature and return codes of that function.•It is important that the calling program provides the required scratch RAM buffersfor the BIOS and the proper stack size as specified in the interface definition.•The calling program should read any update data that already exists in the BIOSin order to make decisions about the appropriateness of loading the update.
TheBIOS must refuse to overwrite a newer update with an older version. The updateheader contains information about version and processor specifics for the callingprogram to make an intelligent decision about loading.•There can be no ambiguous updates. The BIOS must refuse to allow multipleupdates for the same CPU to exist at the same time; it also must refuse to loadupdates for processors that don’t exist on the system.•The calling application should implement a verify function that is run after theupdate write function successfully completes.
This function reads back theupdate and verifies that the BIOS returned an image identical to the one that waswritten.Example 9-12 represents a calling program.9-52 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONExample 9-12. INT 15 DO42 Calling Program Pseudo-code//// We must be in real mode//If the system is not in Real mode exit//// Detect presence of Genuine Intel processor(s) that can be updated// using(CPUID)//If no Intel processors exist that can be updated exit//// Detect the presence of the Intel microcode update extensions//If the BIOS fails the PresenceTestexit//// If the APIC is enabled, see if any other processors are out there//Read IA32_APICBASEIf APIC enabled{Send Broadcast Message to all processors except self via APICHave all processors execute CPUID, record the Processor Signature(i.e.,Extended Family, Extended Model, Type, Family, Model,Stepping)Have all processors read IA32_PLATFORM_ID[52:50], record PlatformId BitsIf current processor cannot be updatedexit}//// Determine the number of unique update blocks needed for this system//NumBlocks = 0For each processor{If ((this is a unique processor stepping) AND(we have a unique update in the database for this processor)){Checksum the update from the database;If Checksum failsexitNumBlocks ← NumBlocks + size of microcode update / 2048}}//Vol.
3 9-53PROCESSOR MANAGEMENT AND INITIALIZATION// Do we have enough update slots for all CPUs?//If there are more blocks required to support the unique processorsteppings than update blocks provided by the BIOS exit//// Do we need any update blocks at all? If not, we are done//If (NumBlocks == 0)exit//// Record updates for processors in NVRAM.//For (I=0; I<NumBlocks; I++){//// Load each Update//Issue the WriteUpdate functionIf (STORAGE_FULL) returned{Display Error -- BIOS is not managing NVRAM appropriatelyexit}If (INVALID_REVISION) returned{Display Message: More recent update already loaded in NVRAM forthis steppingcontinue}If any other error returned{Display Diagnosticexit}//// Verify the update was loaded correctly//Issue the ReadUpdate functionIf an error occurred{Display Diagnosticexit9-54 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATION}//// Compare the Update read to that written//If (Update read != Update written){Display Diagnosticexit}I ← I + (size of microcode update / 2048)}//// Enable Update Loading, and inform user//Issue the Update Control function with Task = Enable.9.11.8.3Microcode Update FunctionsTable 9-12 defines current Pentium 4, Intel Xeon, and P6 family processor microcodeupdate functions.Table 9-12. Microcode Update FunctionsMicrocode UpdateFunctionFunctionNumberDescriptionRequired/OptionalPresence test00HReturns information about thesupported functions.RequiredWrite update data01HWrites one of the update data areas(slots).RequiredUpdate control02HGlobally controls the loading of updates.RequiredRead update data03HReads one of the update data areas(slots).Required9.11.8.4INT 15H-based InterfaceIntel recommends that a BIOS interface be provided that allows additional microcodeupdates to be added to system flash.
The INT15H interface is the Intel-definedmethod for doing this.The program that calls this interface is responsible for providing three 64-kilobyteRAM areas for BIOS use during calls to the read and write functions. These RAMscratch pads can be used by the BIOS for any purpose, but only for the duration ofthe function call. The calling routine places real mode segments pointing to the RAMblocks in the CX, DX and SI registers.
Calls to functions in this interface must bemade with a minimum of 32 kilobytes of stack available to the BIOS.Vol. 3 9-55PROCESSOR MANAGEMENT AND INITIALIZATIONIn general, each function returns with CF cleared and AH contains the returnedstatus. The general return codes and other constant definitions are listed in Section9.11.8.9, “Return Codes.”The OEM error field (AL) is provided for the OEM to return additional error information specific to the platform. If the BIOS provides no additional information about theerror, OEM error must be set to SUCCESS.
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