Volume 3A System Programming Guide_ Part 1 (794103), страница 102
Текст из файла (страница 102)
This value is zero basedand must be less than the update countreturned from the presence testfunction.Carry FlagCarry SetReturn CodeStatus of the CallOutputCF- Failure - AH contains StatusCarry Clear - All returnvalues are valid.AHVol. 3 9-63PROCESSOR MANAGEMENT AND INITIALIZATIONTable 9-17. Parameters for the Read Microcode Update Data Function (Contd.)ALOEM ErrorAdditional OEM InformationReturn Codes (see Table 9-18 for code definitions)SUCCESSThe function completed successfully.READ_FAILUREThere was a failure because of theinability to read the storage device.UPDATE_NUM_INVALIDUpdate number exceeds the maximumnumber of update blocks implementedby the BIOS.NOT_EMPTYThe specified update block is asubsequent block in use to store a validmicrocode update that spans multipleblocks.The specified block is not a header blockand is not empty.The read function enables the caller to read any microcode update data that alreadyexists in a BIOS and make decisions about the addition of new updates.
As a resultof a successful call, the BIOS copies the microcode update into the location pointedto by ES:DI, with the contents of all Update block(s) that are used to store the specified microcode update.If the specified block is not a header block, but does contain valid data from a microcode update that spans multiple update blocks, then the BIOS must return Failurewith the NOT_EMPTY error code in AH.An update block is considered unused and available for storing a new update if itsHeader Version contains the value 0FFFFFFFFH after return from this function call.The actual implementation of NVRAM storage management is not specified here andis BIOS dependent. As an example, the actual data value used to represent anempty block by the BIOS may be zero, rather than 0FFFFFFFFH.
The BIOS is responsible for translating this information into the header provided by this function.9.11.8.9Return CodesAfter the call has been made, the return codes listed in Table 9-18 are available in theAH register.9-64 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONTable 9-18. Return Code DefinitionsReturn CodeValueDescriptionSUCCESS00HThe function completed successfully.NOT_IMPLEMENTED86HThe function is not implemented.ERASE_FAILURE90HA failure because of the inability to erase the storagedevice.WRITE_FAILURE91HA failure because of the inability to write the storagedevice.READ_FAILURE92HA failure because of the inability to read the storagedevice.STORAGE_FULL93HThe BIOS non-volatile storage area is unable toaccommodate the update because all available updateblocks are filled with updates that are needed forprocessors in the system.CPU_NOT_PRESENT94HThe processor stepping does not currently exist in thesystem.INVALID_HEADER95HThe update header contains a header or loader versionthat is not recognized by the BIOS.INVALID_HEADER_CS96HThe update does not checksum correctly.SECURITY_FAILURE97HThe update was rejected by the processor.INVALID_REVISION98HThe same or more recent revision of the update existsin the storage device.UPDATE_NUM_INVALID99HThe update number exceeds the maximum number ofupdate blocks implemented by the BIOS.NOT_EMPTY9AHThe specified update block is a subsequent block in useto store a valid microcode update that spans multipleblocks.The specified block is not a header block and is notempty.Vol.
3 9-65PROCESSOR MANAGEMENT AND INITIALIZATION9-66 Vol. 3CHAPTER 10MEMORY CACHE CONTROLThis chapter describes the memory cache and cache control mechanisms, the TLBs,and the store buffer in Intel 64 and IA-32 processors. It also describes the memorytype range registers (MTRRs) introduced in the P6 family processors and how theyare used to control caching of physical memory locations.10.1INTERNAL CACHES, TLBS, AND BUFFERSThe Intel 64 and IA-32 architectures support cache, translation look aside buffers(TLBs), and a store buffer for temporary on-chip (and external) storage of instructions and data. (Figure 10-1 shows the arrangement of caches, TLBs, and the storebuffer for the Pentium 4 and Intel Xeon processors.) Table 10-1 shows the characteristics of these caches and buffers for the Pentium 4, Intel Xeon, P6 family, andPentium processors.
The sizes and characteristics of these units are machinespecific and may change in future versions of the processor. The CPUIDinstruction returns the sizes and characteristics of the caches and buffers for theprocessor on which the instruction is executed. See “CPUID—CPU Identification” inChapter 3, “Instruction Set Reference, A-M,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.PhysicalMemorySystem Bus(External)L3 Cache†L2 CacheData CacheUnit (L1)InstructionTLBsBus Interface UnitData TLBsInstruction DecoderTrace CacheStore Buffer† Intel Xeon processors onlyFigure 10-1. Cache Structure of the Pentium 4 and Intel Xeon ProcessorsVol.
3 10-1MEMORY CACHE CONTROLTable 10-1. Characteristics of the Caches, TLBs, Store Buffer, andWrite Combining Buffer in Intel 64 and IA-32 ProcessorsCache or Buffer1Trace CacheCharacteristics• Pentium 4 and Intel Xeon processors: 12 Kμops, 8-way set associative.• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, Pentium M processor: notimplemented.• P6 family and Pentium processors: not implemented.L1 Instruction Cache • Pentium 4 and Intel Xeon processors: not implemented.• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, Pentium M processor:32-KByte, 8-way set associative.• P6 family and Pentium processors: 8- or 16-KByte, 4-way set associative,32-byte cache line size; 2-way set associative for earlier Pentiumprocessors.L1 Data Cache• Pentium 4 and Intel Xeon processors: 8-KByte, 4-way set associative,64-byte cache line size.• Pentium 4 and Intel Xeon processors: 16-KByte, 8-way set associative,64-byte cache line size.• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, Pentium M processor: 32KByte, 8-way set associative, 64-byte cache line size.• P6 family processors: 16-KByte, 4-way set associative, 32-byte cacheline size; 8-KBytes, 2-way set associative for earlier P6 familyprocessors.• Pentium processors: 16-KByte, 4-way set associative, 32-byte cache linesize; 8-KByte, 2-way set associative for earlier Pentium processors.L2 Unified Cache• Intel Core 2 Duo processor: up to 4-MByte, 16-way set associative,64-byte cache line size.• Intel Core Duo, Intel Core Solo processors: 2-MByte, 8-way setassociative, 64-byte cache line size• Pentium 4 and Intel Xeon processors: 256, 512, 1024, or 2048-KByte, 8way set associative, 64-byte cache line size, 128-byte sector size.• Pentium M processor: 1 or 2-MByte, 8-way set associative, 64-bytecache line size.• P6 family processors: 128-KByte, 256-KByte, 512-KByte, 1-MByte, or 2MByte, 4-way set associative, 32-byte cache line size.• Pentium processor (external optional): System specific, typically 256- or512-KByte, 4-way set associative, 32-byte cache line size.L3 Unified Cache• Intel Xeon processors: 512-KByte, 1-MByte, 2-MByte, or 4-MByte, 8-wayset associative, 64-byte cache line size, 128-byte sector size.Instruction TLB(4-KByte Pages)• Pentium 4 and Intel Xeon processors: 128 entries, 4-way set associative.• Intel Core 2 Duo, Intel Core Duo, Intel Core Solo processors, Pentium Mprocessor: 128 entries, 4-way set associative.• P6 family processors: 32 entries, 4-way set associative.• Pentium processor: 32 entries, 4-way set associative; fully setassociative for Pentium processors with MMX technology.10-2 Vol.
3MEMORY CACHE CONTROLTable 10-1. Characteristics of the Caches, TLBs, Store Buffer, andWrite Combining Buffer in Intel 64 and IA-32 Processors (Contd.)Cache or BufferCharacteristicsData TLB (4-KBytePages)• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 256 entries, 4ways.• Pentium 4 and Intel Xeon processors: 64 entries, fully set associative;shared with large page data TLBs.• Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128entries, 4-way set associative.• Pentium and P6 family processors: 64 entries, 4-way set associative;fully set, associative for Pentium processors with MMX technology.Instruction TLB(Large Pages)• Intel Core 2 Duo processors: 4 entries, 4 ways.• Pentium 4 and Intel Xeon processors: large pages are fragmented.• Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entries, fullyassociative.• P6 family processors: 2 entries, fully associative.• Pentium processor: Uses same TLB as used for 4-KByte pages.Data TLB (LargePages)• Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 32 entries, 4ways.• Pentium 4 and Intel Xeon processors: 64 entries, fully set associative;shared with small page data TLBs.• Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entries, fullyassociative.• P6 family processors: 8 entries, 4-way set associative.• Pentium processor: 8 entries, 4-way set associative; uses same TLB asused for 4-KByte pages in Pentium processors with MMX technology.Store Buffer•••••Intel Core 2 Duo processors: 20 entries.Pentium 4 and Intel Xeon processors: 24 entries.Pentium M processor: 16 entries.P6 family processors: 12 entries.Pentium processor: 2 buffers, 1 entry each (Pentium processors withMMX technology have 4 buffers for 4 entries).Write Combining(WC) Buffer••••Intel Core 2 Duo processors: 8 entries.Pentium 4 and Intel Xeon processors: 6 or 8 entries.Intel Core Duo, Intel Core Solo, Pentium M processors: 6 entries.P6 family processors: 4 entries.NOTES:1 Introduced to the IA-32 architecture in the Pentium 4 and Intel Xeon processors.Intel 64 and IA-32 processors may implement four types of caches: the trace cache,the level 1 (L1) cache, the level 2 (L2) cache, and the level 3 (L3) cache.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
