Volume 3A System Programming Guide_ Part 1 (794103), страница 98
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That includes the extended signature count,extended processor signature table checksum, 12 reserved bytes and the nprocessor signature structures. A valid extended signature table exists when theresult of a DWORD checksum is 00000000H.Table 9-8. Extended Processor Signature Table Header StructureExtended Signature Count ‘n’Extended Processor Signature Table ChecksumReserved (12 Bytes)Data Size + 48Data Size + 52Data Size + 56Table 9-9. Processor Signature StructureProcessor Signature[n]Processor Flags[n]Checksum[n]9.11.3Data Size + 68 + (n * 12)Data Size + 72 + (n * 12)Data Size + 76 + (n * 12)Processor IdentificationEach microcode update is designed to for a specific processor or set of processors. Todetermine the correct microcode update to load, software must ensure that one ofthe processor signatures embedded in the microcode update matches the 32-bitprocessor signature returned by the CPUID instruction when executed by the targetprocessor with EAX = 1.
Attempting to load a microcode update that does not matchVol. 3 9-41PROCESSOR MANAGEMENT AND INITIALIZATIONa processor signature embedded in the microcode update with the processor signature returned by CPUID will cause the BIOS to reject the update.Example 9-5 shows how to check for a valid processor signature match between theprocessor and microcode update.Example 9-5. Pseudo Code to Validate the Processor SignatureProcessorSignature ← CPUID(1):EAXIf (Update.HeaderVersion == 00000001h){// first check the ProcessorSignature fieldIf (ProcessorSignature == Update.ProcessorSignature)Success// if extended signature is presentElse If (Update.TotalSize > (Update.DataSize + 48)){//// Assume the Data Size has been used to calculate the// location of Update.ProcessorSignature[0].//For (N ← 0; ((N < Update.ExtendedSignatureCount) AND(ProcessorSignature != Update.ProcessorSignature[N])); N++);// if the loops ended when the iteration count is// less than the number of processor signatures in// the table, we have a matchIf (N < Update.ExtendedSignatureCount)SuccessElseFail}ElseFailElseFail9.11.4Platform IdentificationIn addition to verifying the processor signature, the intended processor platform typemust be determined to properly target the microcode update.
The intendedprocessor platform type is determined by reading the IA32_PLATFORM_ID register,(MSR 17H). This 64-bit register must be read using the RDMSR instruction.9-42 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONThe three platform ID bits, when read as a binary coded decimal (BCD) number, indicate the bit position in the microcode update header’s processor flags field associatedwith the installed processor. The processor flags in the 48-byte header and theprocessor flags field associated with the extended processor signature structuresmay have multiple bits set. Each set bit represents a different platform ID that theupdate supports.Register Name:MSR Address:Access:IA32_PLATFORM_ID017HRead OnlyIA32_PLATFORM_ID is a 64-bit register accessed only when referenced as a Qword through aRDMSR instruction.Table 9-10.
Processor FlagsBit63:5352:50DescriptionsReservedPlatform Id Bits (RO). The field gives information concerning the intended platform forthe processor. See also Table 9-7.520000111149:051001100115001010101Processor Flag 0Processor Flag 1Processor Flag 2Processor Flag 3Processor Flag 4Processor Flag 5Processor Flag 6Processor Flag 7ReservedTo validate the platform information, software may implement an algorithm similar tothe algorithms in Example 9-6.Example 9-6.
Pseudo Code Example of Processor Flags TestFlag ← 1 << IA32_PLATFORM_ID[52:50]If (Update.HeaderVersion == 00000001h){If (Update.ProcessorFlags & Flag){Load UpdateVol. 3 9-43PROCESSOR MANAGEMENT AND INITIALIZATION}Else{//// Assume the Data Size has been used to calculate the// location of Update.ProcessorSignature[N] and a match// on Update.ProcessorSignature[N] has already succeeded//If (Update.ProcessorFlags[n] & Flag){Load Update}}}9.11.5Microcode Update ChecksumEach microcode update contains a DWORD checksum located in the update header. Itis software’s responsibility to ensure that a microcode update is not corrupt.
To checkfor a corrupt microcode update, software must perform a unsigned DWORD (32-bit)checksum of the microcode update. Even though some fields are signed, thechecksum procedure treats all DWORDs as unsigned. Microcode updates with aheader version equal to 00000001H must sum all DWORDs that comprise the microcode update. A valid checksum check will yield a value of 00000000H. Any othervalue indicates the microcode update is corrupt and should not be loaded.The checksum algorithm shown by the pseudo code in Example 9-7 treats the microcode update as an array of unsigned DWORDs.
If the data size DWORD field at byteoffset 32 equals 00000000H, the size of the encrypted data is 2000 bytes, resultingin 500 DWORDs. Otherwise the microcode update size in DWORDs = (Total Size / 4),where the total size is a multiple of 1024 bytes (1 KBytes).Example 9-7. Pseudo Code Example of Checksum TestN ← 512If (Update.DataSize != 00000000H)N ← Update.TotalSize / 4ChkSum ← 0For (I ← 0; I < N; I++){ChkSum ← ChkSum + MicrocodeUpdate[I]}9-44 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATIONIf (ChkSum == 00000000H)SuccessElseFail9.11.6Microcode Update LoaderThis section describes an update loader used to load an update into a Pentium 4, IntelXeon, or P6 family processor. It also discusses the requirements placed on the BIOSto ensure proper loading. The update loader described contains the minimal instructions needed to load an update.
The specific instruction sequence that is required toload an update is dependent upon the loader revision field contained within theupdate header. This revision is expected to change infrequently (potentially, onlywhen new processor models are introduced).Example 9-8 below represents the update loader with a loader revision of00000001H. Note that the microcode update must be aligned on a 16-byte boundaryand the size of the microcode update must be 1-KByte granular.Example 9-8. Assembly Code Example of Simple Microcode Update Loadermov ecx,79hxor eax,eaxxor ebx,ebxmov ax,csshl eax,4mov bx,offset Updateadd eax,ebxadd eax,48dxor edx,edxWRMSR;;;;MSR to read in ECXclear EAXclear EBXSegment of microcode update; Offset of microcode update; Linear Address of Update in EAX; Offset of the Update Data within the Update; Zero in EDX; microcode update triggerThe loader shown in Example 9-8 assumes that update is the address of a microcodeupdate (header and data) embedded within the code segment of the BIOS.
It alsoassumes that the processor is operating in real mode. The data may reside anywherein memory, aligned on a 16-byte boundary, that is accessible by the processor withinits current operating mode.Before the BIOS executes the microcode update trigger (WRMSR) instruction, thefollowing must be true:•In 64-bit mode, EAX contains the lower 32-bits of the microcode update linearaddress. In protected mode, EAX contains the full 32-bit linear address of themicrocode update.•In 64-bit mode, EDX contains the upper 32-bits of the microcode update linearaddress.
In protected mode, EDX equals zero.Vol. 3 9-45PROCESSOR MANAGEMENT AND INITIALIZATION•ECX contains 79H (address of IA32_BIOS_UPDT_TRIG).Other requirements are:•If the update is loaded while the processor is in real mode, then the update datamay not cross a segment boundary.•If the update is loaded while the processor is in real mode, then the update datamay not exceed a segment limit.••If paging is enabled, pages that are currently present must map the update data.The microcode update data requires a 16-byte boundary alignment.9.11.6.1Hard Resets in Update LoadingThe effects of a loaded update are cleared from the processor upon a hard reset.Therefore, each time a hard reset is asserted during the BIOS POST, the update mustbe reloaded on all processors that observed the reset. The effects of a loaded updateare, however, maintained across a processor INIT. There are no side effects causedby loading an update into a processor multiple times.9.11.6.2Update in a Multiprocessor SystemA multiprocessor (MP) system requires loading each processor with update dataappropriate for its CPUID and platform ID bits.
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