Volume 3A System Programming Guide_ Part 1 (794103), страница 93
Текст из файла (страница 93)
They allow the type of caching (or no caching) to bespecified in system memory for selected physical address ranges. They allowmemory accesses to be optimized for various types of memory such as RAM, ROM,frame buffer memory, and memory-mapped I/O devices.In general, initializing the MTRRs is normally handled by the software initializationcode or BIOS and is not an operating system or executive function. At the very least,all the MTRRs must be cleared to 0, which selects the uncached (UC) memory type.Vol. 3 9-9PROCESSOR MANAGEMENT AND INITIALIZATIONSee Section 10.11, “Memory Type Range Registers (MTRRs),” for detailed information on the MTRRs.9.6INITIALIZING SSE/SSE2/SSE3/SSSE3 EXTENSIONSFor processors that contain SSE/SSE2/SSE3/SSSE3 extensions, steps must be takenwhen initializing the processor to allow execution of these instructions.1.
Check the CPUID feature flags for the presence of the SSE/SSE2/SSE3/SSSE3extensions (respectively: EDX bits 25 and 26, ECX bit 0 and 9) and support forthe FXSAVE and FXRSTOR instructions (EDX bit 24). Also check for support forthe CLFLUSH instruction (EDX bit 19). The CPUID feature flags are loaded in theEDX and ECX registers when the CPUID instruction is executed with a 1 in theEAX register.2. Set the OSFXSR flag (bit 9 in control register CR4) to indicate that the operatingsystem supports saving and restoring the SSE/SSE2/SSE3/SSSE3 executionenvironment (XXM and MXCSR registers) with the FXSAVE and FXRSTOR instructions, respectively. See Section 2.5, “Control Registers,” for a description of theOSFXSR flag.3.
Set the OSXMMEXCPT flag (bit 10 in control register CR4) to indicate that theoperating system supports the handling of SSE/SSE2/SSE3 SIMD floating-pointexceptions (#XF). See Section 2.5, “Control Registers,” for a description of theOSXMMEXCPT flag.4. Set the mask bits and flags in the MXCSR register according to the mode ofoperation desired for SSE/SSE2/SSE3 SIMD floating-point instructions. See“MXCSR Control and Status Register” in Chapter 10, “Programming withStreaming SIMD Extensions (SSE),” of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for a detailed description of the bits andflags in the MXCSR register.9.7SOFTWARE INITIALIZATION FOR REAL-ADDRESSMODE OPERATIONFollowing a hardware reset (either through a power-up or the assertion of theRESET# pin) the processor is placed in real-address mode and begins executing software initialization code from physical address FFFFFFF0H.
Software initialization codemust first set up the necessary data structures for handling basic system functions,such as a real-mode IDT for handling interrupts and exceptions. If the processor is toremain in real-address mode, software must then load additional operating-systemor executive code modules and data structures to allow reliable execution of application programs in real-address mode.If the processor is going to operate in protected mode, software must load the necessary data structures to operate in protected mode and then switch to protected9-10 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATIONmode. The protected-mode data structures that must be loaded are described inSection 9.8, “Software Initialization for Protected-Mode Operation.”9.7.1Real-Address Mode IDTIn real-address mode, the only system data structure that must be loaded intomemory is the IDT (also called the “interrupt vector table”).
By default, the addressof the base of the IDT is physical address 0H. This address can be changed by usingthe LIDT instruction to change the base address value in the IDTR. Software initialization code needs to load interrupt- and exception-handler pointers into the IDTbefore interrupts can be enabled.The actual interrupt- and exception-handler code can be contained either in EPROMor RAM; however, the code must be located within the 1-MByte addressable range ofthe processor in real-address mode.
If the handler code is to be stored in RAM, itmust be loaded along with the IDT.9.7.2NMI Interrupt HandlingThe NMI interrupt is always enabled (except when multiple NMIs are nested). If theIDT and the NMI interrupt handler need to be loaded into RAM, there will be a periodof time following hardware reset when an NMI interrupt cannot be handled. Duringthis time, hardware must provide a mechanism to prevent an NMI interrupt fromhalting code execution until the IDT and the necessary NMI handler software isloaded. Here are two examples of how NMIs can be handled during the initial statesof processor initialization:•A simple IDT and NMI interrupt handler can be provided in EPROM.
This allows anNMI interrupt to be handled immediately after reset initialization.•The system hardware can provide a mechanism to enable and disable NMIs bypassing the NMI# signal through an AND gate controlled by a flag in an I/O port.Hardware can clear the flag when the processor is reset, and software can set theflag when it is ready to handle NMI interrupts.9.8SOFTWARE INITIALIZATION FOR PROTECTED-MODEOPERATIONThe processor is placed in real-address mode following a hardware reset. At thispoint in the initialization process, some basic data structures and code modules mustbe loaded into physical memory to support further initialization of the processor, asdescribed in Section 9.7, “Software Initialization for Real-Address Mode Operation.”Before the processor can be switched to protected mode, the software initializationcode must load a minimum number of protected mode data structures and codeVol.
3 9-11PROCESSOR MANAGEMENT AND INITIALIZATIONmodules into memory to support reliable operation of the processor in protectedmode. These data structures include the following:••••••A IDT.•One or more code modules that contain the necessary interrupt and exceptionhandlers.A GDT.A TSS.(Optional) An LDT.If paging is to be used, at least one page directory and one page table.A code segment that contains the code to be executed when the processorswitches to protected mode.Software initialization code must also initialize the following system registers beforethe processor can be switched to protected mode:••The GDTR.••Control registers CR1 through CR4.(Optional.) The IDTR. This register can also be initialized immediately afterswitching to protected mode, prior to enabling interrupts.(Pentium 4, Intel Xeon, and P6 family processors only.) The memory type rangeregisters (MTRRs).With these data structures, code modules, and system registers initialized, theprocessor can be switched to protected mode by loading control register CR0 with avalue that sets the PE flag (bit 0).9.8.1Protected-Mode System Data StructuresThe contents of the protected-mode system data structures loaded into memoryduring software initialization, depend largely on the type of memory managementthe protected-mode operating-system or executive is going to support: flat, flat withpaging, segmented, or segmented with paging.To implement a flat memory model without paging, software initialization code mustat a minimum load a GDT with one code and one data-segment descriptor.
A nulldescriptor in the first GDT entry is also required. The stack can be placed in a normalread/write data segment, so no dedicated descriptor for the stack is required. A flatmemory model with paging also requires a page directory and at least one page table(unless all pages are 4 MBytes in which case only a page directory is required). SeeSection 9.8.3, “Initializing Paging.”Before the GDT can be used, the base address and limit for the GDT must be loadedinto the GDTR register using an LGDT instruction.A multi-segmented model may require additional segments for the operating system,as well as segments and LDTs for each application program. LDTs require segment9-12 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATIONdescriptors in the GDT. Some operating systems allocate new segments and LDTs asthey are needed. This provides maximum flexibility for handling a dynamic programming environment. However, many operating systems use a single LDT for all tasks,allocating GDT entries in advance. An embedded system, such as a processcontroller, might pre-allocate a fixed number of segments and LDTs for a fixednumber of application programs.
This would be a simple and efficient way to structure the software environment of a real-time system.9.8.2Initializing Protected-Mode Exceptions and InterruptsSoftware initialization code must at a minimum load a protected-mode IDT with gatedescriptor for each exception vector that the processor can generate. If interrupt ortrap gates are used, the gate descriptors can all point to the same code segment,which contains the necessary exception handlers. If task gates are used, one TSSand accompanying code, data, and task segments are required for each exceptionhandler called with a task gate.If hardware allows interrupts to be generated, gate descriptors must be provided inthe IDT for one or more interrupt handlers.Before the IDT can be used, the base address and limit for the IDT must be loadedinto the IDTR register using an LIDT instruction.
This operation is typically carried outimmediately after switching to protected mode.9.8.3Initializing PagingPaging is controlled by the PG flag in control register CR0. When this flag is clear (itsstate following a hardware reset), the paging mechanism is turned off; when it is set,paging is enabled. Before setting the PG flag, the following data structures and registers must be initialized:•Software must load at least one page directory and one page table into physicalmemory. The page table can be eliminated if the page directory contains adirectory entry pointing to itself (here, the page directory and page table residein the same page), or if only 4-MByte pages are used.•Control register CR3 (also called the PDBR register) is loaded with the physicalbase address of the page directory.•(Optional) Software may provide one set of code and data descriptors in the GDTor in an LDT for supervisor mode and another set for user mode.With this paging initialization complete, paging is enabled and the processor isswitched to protected mode at the same time by loading control register CR0 with animage in which the PG and PE flags are set.
(Paging cannot be enabled before theprocessor is switched to protected mode.)Vol. 3 9-13PROCESSOR MANAGEMENT AND INITIALIZATION9.8.4Initializing MultitaskingIf the multitasking mechanism is not going to be used and changes between privilegelevels are not allowed, it is not necessary load a TSS into memory or to initialize thetask register.If the multitasking mechanism is going to be used and/or changes between privilegelevels are allowed, software initialization code must load at least one TSS and anaccompanying TSS descriptor. (A TSS is required to change privilege levels becausepointers to the privileged-level 0, 1, and 2 stack segments and the stack pointers forthese stacks are obtained from the TSS.) TSS descriptors must not be marked asbusy when they are created; they should be marked busy by the processor only as aside-effect of performing a task switch.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
