Volume 3A System Programming Guide_ Part 1 (794103), страница 89
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The 256 bits inthese registers represent the 256 possible vectors; vectors 0 through 15 arereserved by the APIC (see also: Section 8.5.2, “Valid Interrupt Vectors”).NOTEAll interrupts with an NMI, SMI, INIT, ExtINT, start-up, or INITdeassert delivery mode bypass the IRR and ISR registers and aresent directly to the processor core for servicing.8-40 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)25516 150ReservedIRRReservedISRReservedTMRAddresses: IRR FEE0 0200H - FEE0 0270HISR FEE0 0100H - FEE0 0170HTMR FEE0 0180H - FEE0 01F0HValue after reset: 0HFigure 8-20. IRR, ISR and TMR RegistersThe IRR contains the active interrupt requests that have been accepted, but not yetdispatched to the processor for servicing. When the local APIC accepts an interrupt,it sets the bit in the IRR that corresponds the vector of the accepted interrupt.
Whenthe processor core is ready to handle the next interrupt, the local APIC clears thehighest priority IRR bit that is set and sets the corresponding ISR bit. The vector forthe highest priority bit set in the ISR is then dispatched to the processor core forservicing.While the processor is servicing the highest priority interrupt, the local APIC can sendadditional fixed interrupts by setting bits in the IRR. When the interrupt serviceroutine issues a write to the EOI register (see Section 8.8.5, “Signaling InterruptServicing Completion”), the local APIC responds by clearing the highest priority ISRbit that is set. It then repeats the process of clearing the highest priority bit in the IRRand setting the corresponding bit in the ISR. The processor core then beginsexecuting the service routing for the highest priority bit set in the ISR.If more than one interrupt is generated with the same vector number, the local APICcan set the bit for the vector both in the IRR and the ISR.
This means that for thePentium 4 and Intel Xeon processors, the IRR and ISR can queue two interrupts foreach interrupt vector: one in the IRR and one in the ISR. Any additional interruptsissued for the same interrupt vector are collapsed into the single bit in the IRR.For the P6 family and Pentium processors, the IRR and ISR registers can queue nomore than two interrupts per priority level, and will reject other interrupts that arereceived within the same priority level.If the local APIC receives an interrupt with a priority higher than that of the interruptcurrently in serviced, and interrupts are enabled in the processor core, the local APICdispatches the higher priority interrupt to the processor immediately (withoutwaiting for a write to the EOI register).
The currently executing interrupt handler isthen interrupted so the higher-priority interrupt can be handled. When the handlingof the higher-priority interrupt has been completed, the servicing of the interruptedinterrupt is resumed.The trigger mode register (TMR) indicates the trigger mode of the interrupt (seeFigure 8-20). Upon acceptance of an interrupt into the IRR, the corresponding TMRVol.
3 8-41ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)bit is cleared for edge-triggered interrupts and set for level-triggered interrupts. If aTMR bit is set when an EOI cycle for its corresponding interrupt vector is generated,an EOI message is sent to all I/O APICs.8.8.5Signaling Interrupt Servicing CompletionFor all interrupts except those delivered with the NMI, SMI, INIT, ExtINT, the startup, or INIT-Deassert delivery mode, the interrupt handler must include a write to theend-of-interrupt (EOI) register (see Figure 8-21). This write must occur at the end ofthe handler routine, sometime before the IRET instruction.
This action indicates thatthe servicing of the current interrupt is complete and the local APIC can issue thenext interrupt from the ISR.310Address: 0FEE0 00B0HValue after reset: 0HFigure 8-21. EOI RegisterUpon receiving and EOI, the APIC clears the highest priority bit in the ISR anddispatches the next highest priority interrupt to the processor. If the terminatedinterrupt was a level-triggered interrupt, the local APIC also sends an end-of-interrupt message to all I/O APICs.For future compatibility, the software is requested to issue the end-of-interruptcommand by writing a value of 0H into the EOI register.8.8.6Task Priority in IA-32e ModeIn IA-32e mode, operating systems can manage the 16 priority classes of externalinterrupts (see Section 8.8.3, “Interrupt, Task, and Processor Priority”) explicitlyusing the task priority register (TPR).
Operating systems can use the TPR to temporarily block specific (low-priority) interrupts from interrupting a high-priority task.This is done by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example:•Loading the TPR with a value of 8 (01000B) blocks all interrupts with a priority of8 or less while allowing all interrupts with a priority of nine or more to berecognized.••Loading the TPR with zero enables all external interrupts.Loading the TPR with 0F (01111B) disables all external interrupts.8-42 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)The TPR (shown in Figure 8-18) is cleared to 0 on reset.
In 64-bit mode, software canread and write the TPR using an alternate interface, MOV CR8 instruction. The newpriority level is established when the MOV CR8 instruction completes execution. Software does not need to force serialization after loading the TPR using MOV CR8.Use of the MOV CRn instruction requires a privilege level of 0. Programs running atprivilege level greater than 0 cannot read or write the TPR. An attempt to do soresults in a general-protection exception, #GP(0). The TPR is abstracted from theinterrupt controller (IC), which prioritizes and manages external interrupt delivery tothe processor. The IC can be an external device, such as an APIC or 8259. Typically,the IC provides a priority mechanism similar or identical to the TPR. The IC, however,is considered implementation-dependent with the under-lying priority mechanismssubject to change.
CR8, by contrast, is part of the Intel 64 architecture. Software candepend on this definition remaining unchanged.Figure 8-22 shows the layout of CR8; only the low four bits are used. The remaining60 bits are reserved and must be written with zeros. Failure to do this results in ageneral-protection exception, #GP(0).634 30ReservedValue after reset: 0HFigure 8-22. CR8 Register8.8.6.1Interaction of Task Priorities between CR8 and APICThe first implementation of Intel 64 architecture includes a local advanced programmable interrupt controller (APIC) that is similar to the APIC used with previous IA-32processors.
Some aspects of the local APIC affect the operation of the architecturallydefined task priority register and the programming interface using CR8.Notable CR8 and APIC interactions are:••The processor powers up with the local APIC enabled.•APIC.TPR[bits 7:4] = CR8[bits 3:0], APIC.TPR[bits 3:0] = 0. A read of CR8returns a 64-bit value which is the value of TPR[bits 7:4], zero extended to 64bits.The APIC must be enabled for CR8 to function as the TPR. Writes to CR8 arereflected into the APIC Task Priority Register.There are no ordering mechanisms between direct updates of the APIC.TPR and CR8.Operating software should implement either direct APIC TPR updates or CR8 styleTPR updates but not mix them. Software can use a serializing instruction (forexample, CPUID) to serialize updates between MOV CR8 and stores to the APIC.Vol.
3 8-43ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)8.9SPURIOUS INTERRUPTA special situation may occur when a processor raises its task priority to be greaterthan or equal to the level of the interrupt for which the processor INTR signal iscurrently being asserted. If at the time the INTA cycle is issued, the interrupt thatwas to be dispensed has become masked (programmed by software), the local APICwill deliver a spurious-interrupt vector. Dispensing the spurious-interrupt vector doesnot affect the ISR, so the handler for this vector should return without an EOI.The vector number for the spurious-interrupt vector is specified in the spurious-interrupt vector register (see Figure 8-23). The functions of the fields in this register areas follows:Spurious VectorDetermines the vector number to be delivered to the processorwhen the local APIC generates a spurious vector.(Pentium 4 and Intel Xeon processors.) Bits 0 through 7 of thethis field are programmable by software.(P6 family and Pentium processors).
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