Volume 3A System Programming Guide_ Part 1 (794103), страница 86
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Shorthands are defined for the followingcases: software self interrupt, IPIs to all processors in thesystem including the sender, IPIs to all processors in the systemexcluding the sender.00: (No Shorthand)The destination is specified in the destinationfield.01: (Self)The issuing APIC is the one and only destination of the IPI. This destination shorthand allows software to interrupt the processor onwhich it is executing. An APIC implementation is free to deliver the self-interrupt message internally or to issue the message tothe bus and “snoop” it as with any other IPImessage.10: (All Including Self)The IPI is sent to all processors in the systemincluding the processor sending the IPI.
TheAPIC will broadcast an IPI message with the8-26 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)destination field set to FH for Pentium and P6family processors and to FFH for Pentium 4and Intel Xeon processors.11: (All Excluding Self)The IPI is sent to all processors in a systemwith the exception of the processor sendingthe IPI. The APIC broadcasts a message withthe physical destination mode and destination field set to 0xFH for Pentium and P6family processors and to 0xFFH for Pentium4 and Intel Xeon processors.
Support for thisdestination shorthand in conjunction withthe lowest-priority delivery mode is modelspecific. For Pentium 4 and Intel Xeon processors, when this shorthand is used together with lowest priority delivery mode, the IPImay be redirected back to the issuing processor.DestinationSpecifies the target processor or processors. This field is onlyused when the destination shorthand field is set to 00B. If thedestination mode is set to physical, then bits 56 through 59contain the APIC ID of the target processor for Pentium and P6family processors and bits 56 through 63 contain the APIC ID ofthe target processor the for Pentium 4 and Intel Xeon processors.
If the destination mode is set to logical, the interpretationof the 8-bit destination field depends on the settings of the DFRand LDR registers of the local APICs in all the processors in thesystem (see Section 8.6.2, “Determining IPI Destination”).Not all combinations of options for the ICR are valid. Table 8-3 shows the valid combinations for the fields in the ICR for the Pentium 4 and Intel Xeon processors; Table8-4 shows the valid combinations for the fields in the ICR for the P6 family processors.
Also note that the lower half of the ICR may not be preserved over transitionsto the deepest C-States.Table 8-3. Valid Combinations for the Pentium 4 and Intel Xeon Processors’Local xAPIC Interrupt Command RegisterDestinationShorthandValid/InvalidTriggerModeDelivery ModeDestinationModeNo ShorthandValidEdgeAll Modes1Physical or LogicalNo ShorthandInvalid2LevelAll ModesPhysical or LogicalSelfValidEdgeFixedX3SelfInvalid2LevelFixedXVol. 3 8-27ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Table 8-3. Valid Combinations for the Pentium 4 and Intel Xeon Processors’Local xAPIC Interrupt Command Register (Contd.)DestinationShorthandValid/InvalidTriggerModeDestinationModeSelfInvalidXLowest Priority, NMI, INIT, SMI, Start- XUpAll Including SelfValidEdgeFixedXAll Including SelfInvalid2LevelFixedXAll Including SelfInvalidXAll ExcludingSelfValidEdgeLowest Priority, NMI, INIT, SMI, Start- XUpFixed, Lowest Priority1,4, NMI, INIT, XSMI, Start-UpAll ExcludingSelfInvalid2LevelDelivery ModeFIxed, Lowest Priority4, NMI, INIT,SMI, Start-UpXNOTES:1.
The ability of a processor to send a lowest priority IPI is model specific.2. For these interrupts, if the trigger mode bit is 1 (Level), the local xAPIC will override the bit setting and issue the interrupt as an edge triggered interrupt.3. X means the setting is ignored.4. When using the “lowest priority” delivery mode and the “all excluding self” destination, the IPIcan be redirected back to the issuing APIC, which is essentially the same as the “all includingself” destination mode.Table 8-4. Valid Combinations for the P6 Family Processors’Local APIC Interrupt Command RegisterDestinationShorthandNo ShorthandNo ShorthandValid/InvalidValidTriggerModeEdgeDelivery ModeDestination Mode1Physical or LogicalAll ModesValid2LevelFixed, Lowest3LevelINITPhysical or LogicalEdgeFixedX4LevelFixedXNo ShorthandValidSelfValidSelf15Priority1,NMIPhysical or LogicalSelfInvalidXLowest Priority, NMI, INIT,SMI, Start-UpXAll including SelfValidEdgeFixedXAll including SelfValid2LevelFixedXXLowest Priority, NMI, INIT,SMI, Start-UpXAll including Self8-28 Vol.
3Invalid5ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Table 8-4. Valid Combinations for the P6 Family Processors’Local APIC Interrupt Command Register (Contd.)DestinationShorthandValid/InvalidAll excluding SelfAll excluding SelfValidTriggerModeEdge2Valid5Delivery ModeAllDestination ModeModes1X1LevelFixed, Lowest Priority , NMIXAll excluding SelfInvalidLevelSMI, Start-UpXAll excluding SelfValid3LevelINITXXInvalid5LevelSMI, Start-UpXNOTES:1. The ability of a processor to send a lowest priority IPI is model specific.2. Treated as edge triggered if level bit is set to 1, otherwise ignored.3.
Treated as edge triggered when Level bit is set to 1; treated as “INIT Level Deassert” messagewhen level bit is set to 0 (deassert). Only INIT level deassert messages are allowed to have thelevel bit set to 0. For all other messages the level bit must be set to 1.4. X means the setting is ignored.5. The behavior of the APIC is undefined.8.6.2Determining IPI DestinationThe destination of an IPI can be one, all, or a subset (group) of the processors on thesystem bus. The sender of the IPI specifies the destination of an IPI with thefollowing APIC registers and fields within the registers:•ICR Register — The following fields in the ICR register are used to specify thedestination of an IPI:— Destination Mode — Selects one of two destination modes (physical orlogical).— Destination Field — In physical destination mode, used to specify the APICID of the destination processor; in logical destination mode, used to specify amessage destination address (MDA) that can be used to select specificprocessors in clusters.— Destination Shorthand — A quick method of specifying all processors, allexcluding self, or self as the destination.— Delivery mode, Lowest Priority — Architecturally specifies that a lowestpriority arbitration mechanism be used to select a destination processor froma specified group of processors.
The ability of a processor to send a lowestpriority IPI is model specific and should be avoided by BIOS and operatingsystem software.•Local destination register (LDR) — Used in conjunction with the logicaldestination mode and MDAs to select the destination processors.Vol. 3 8-29ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)•Destination format register (DFR) — Used in conjunction with the logicaldestination mode and MDAs to select the destination processors.How the ICR, LDR, and DFR are used to select an IPI destination depends on thedestination mode used: physical, logical, broadcast/self, or lowest-priority deliverymode. These destination modes are described in the following sections.8.6.2.1Physical Destination ModeIn physical destination mode, the destination processor is specified by its local APICID (see Section 8.4.6, “Local APIC ID”). For Pentium 4 and Intel Xeon processors,either a single destination (local APIC IDs 00H through FEH) or a broadcast to allAPICs (the APIC ID is FFH) may be specified in physical destination mode.A broadcast IPI (bits 28-31 of the MDA are 1's) or I/O subsystem initiated interruptwith lowest priority delivery mode is not supported in physical destination mode andmust not be configured by software.
Also, for any non-broadcast IPI or I/Osubsystem initiated interrupt with lowest priority delivery mode, software mustensure that APICs defined in the interrupt address are present and enabled to receiveinterrupts.For the P6 family and Pentium processors, a single destination is specified in physicaldestination mode with a local APIC ID of 0H through 0EH, allowing up to 15 localAPICs to be addressed on the APIC bus. A broadcast to all local APICs is specified with0FH.NOTEThe number of local APICs that can be addressed on the system busmay be restricted by hardware.8.6.2.2Logical Destination ModeIn logical destination mode, IPI destination is specified using an 8-bit message destination address (MDA), which is entered in the destination field of the ICR.
Uponreceiving an IPI message that was sent using logical destination mode, a local APICcompares the MDA in the message with the values in its LDR and DFR to determine ifit should accept and handle the IPI. For both configurations of logical destinationmode, when combined with lowest priority delivery mode, software is responsible forensuring that all of the local APICs included in or addressed by the IPI or I/Osubsystem interrupt are present and enabled to receive the interrupt.Figure 8-13 shows the layout of the logical destination register (LDR). The 8-bitlogical APIC ID field in this register is used to create an identifier that can becompared with the MDA.8-30 Vol.
3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)NOTEThe logical APIC ID should not be confused with the local APIC ID thatis contained in the local APIC ID register.31024 23Logical APIC IDReservedAddress: 0FEE0 00D0HValue after reset: 0000 0000HFigure 8-13.
Logical Destination Register (LDR)Figure 8-14 shows the layout of the destination format register (DFR). The 4-bitmodel field in this register selects one of two models (flat or cluster) that can be usedto interpret the MDA when using logical destination mode.31028ModelReserved (All 1s)Flat model: 1111BCluster model: 0000BAddress: 0FEE0 00E0HValue after reset: FFFF FFFFHFigure 8-14. Destination Format Register (DFR)The interpretation of MDA for the two models is described in the following paragraphs.1. Flat Model — This model is selected by programming DFR bits 28 through 31 to1111. Here, a unique logical APIC ID can be established for up to 8 local APICs bysetting a different bit in the logical APIC ID field of the LDR for each local APIC.
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