Volume 3A System Programming Guide_ Part 1 (794103), страница 83
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Using the APIC global enable/disable flag in the IA32_APIC_BASE MSR (MSRaddress 1BH; see Figure 8-5):— When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent toan IA-32 processor without an on-chip APIC. The CPUID feature flag for theAPIC (see Section 8.4.2, “Presence of the Local APIC”) is also set to 0.— When IA32_APIC_BASE[11] is set to 0, processor APICs based on the 3-wireAPIC bus cannot be generally re-enabled until a system hardware reset. The3-wire bus loses track of arbitration that would be necessary for complete reenabling.
Certain APIC functionality can be enabled (for example:performance and thermal monitoring interrupt generation).8-10 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)— For processors that use Front Side Bus (FSB) delivery of interrupts, softwaremay disable or enable the APIC by setting and resettingIA32_APIC_BASE[11]. A hardware reset is not required to re-start APICfunctionality.— When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC may belost and the APIC may return to the state described in Section 8.4.7.1, “LocalAPIC State After Power-Up or Reset.”2. Using the APIC software enable/disable flag in the spurious-interrupt vectorregister (see Figure 8-23):— If IA32_APIC_BASE[11] is 1, software can temporarily disable a local APIC atany time by clearing the APIC software enable/disable flag in the spuriousinterrupt vector register (see Figure 8-23).
The state of the local APIC whenin this software-disabled state is described in Section 8.4.7.2, “Local APICState After It Has Been Software Disabled.”— When the local APIC is in the software-disabled state, it can be re-enabled atany time by setting the APIC software enable/disable flag to 1.For the Pentium processor, the APICEN pin (which is shared with the PICD1 pin) isused during power-up or RESET to disable the local APIC.Note that each entry in the LVT has a mask bit that can be used to inhibit interruptsfrom being delivered to the processor from selected local interrupt sources (theLINT0 and LINT1 pins, the APIC timer, the performance-monitoring counters, thethermal sensor, and/or the internal APIC error detector).8.4.4Local APIC Status and LocationThe status and location of the local APIC are contained in the IA32_APIC_BASE MSR(see Figure 8-5).
MSR bit functions are described below:•BSP flag, bit 8 ⎯ Indicates if the processor is the bootstrap processor (BSP).See Section 7.5, “Multiple-Processor (MP) Initialization.” Following a power-up orRESET, this flag is set to 1 for the processor selected as the BSP and set to 0 forthe remaining processors (APs).•APIC Global Enable flag, bit 11 ⎯ Enables or disables the local APIC (seeSection 8.4.3, “Enabling or Disabling the Local APIC”). This flag is available in thePentium 4, Intel Xeon, and P6 family processors. It is not guaranteed to beavailable or available at the same location in future Intel 64 or IA-32 processors.•APIC Base field, bits 12 through 35 ⎯ Specifies the base address of the APICregisters. This 24-bit value is extended by 12 bits at the low end to form the baseaddress.
This automatically aligns the address on a 4-KByte boundary. Followinga power-up or RESET, the field is set to FEE0 0000H.•Bits 0 through 7, bits 9 and 10, and bits 36 through 63 in the IA32_APIC_BASEMSR are reserved.Vol. 3 8-11ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)6336 35Reserved12 11 10 9 8 70APIC BaseAPIC Base—Base physical addressAPIC global enable/disableBSP—Processor is BSPReservedFigure 8-5. IA32_APIC_BASE MSR (APIC_BASE_MSR in P6 Family)8.4.5Relocating the Local APIC RegistersThe Pentium 4, Intel Xeon, and P6 family processors permit the starting address ofthe APIC registers to be relocated from FEE00000H to another physical address bymodifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.This extension of the APIC architecture is provided to help resolve conflicts withmemory maps of existing systems and to allow individual processors in an MP systemto map their APIC registers to different locations in physical memory.8.4.6Local APIC IDAt power up, system hardware assigns a unique APIC ID to each local APIC on thesystem bus (for Pentium 4 and Intel Xeon processors) or on the APIC bus (for P6family and Pentium processors).
The hardware assigned APIC ID is based on systemtopology and includes encoding for socket position and cluster information (seeFigure 7-2).In MP systems, the local APIC ID is also used as a processor ID by the BIOS and theoperating system. Some processors permit software to modify the APIC ID. However,the ability of software to modify the APIC ID is processor model specific. Because ofthis, operating system software should avoid writing to the local APIC ID register.
Thevalue returned by bits 31-24 of the EBX register (when the CPUID instruction isexecuted with a source operand value of 1 in the EAX register) is always the InitialAPIC ID (determined by the platform initialization). This is true even if software haschanged the value in the Local APIC ID register.The processor receives the hardware assigned APIC ID (or Initial APIC ID) bysampling pins A11# and A12# and pins BR0# through BR3# (for the Pentium 4, IntelXeon, and P6 family processors) and pins BE0# through BE3# (for the Pentiumprocessor).
The APIC ID latched from these pins is stored in the APIC ID field of thelocal APIC ID register (see Figure 8-6), and is used as the Initial APIC ID for theprocessor.8-12 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Address: 0FEE0 0020HValue after reset: 0000 0000HP6 family and Pentium processors312724APIC ID0ReservedPentium 4 processors, Xeon processors, and later processors3124APIC ID0ReservedFigure 8-6. Local APIC ID RegisterFor the P6 family and Pentium processors, the local APIC ID field in the local APIC IDregister is 4 bits. Encodings 0H through EH can be used to uniquely identify 15different processors connected to the APIC bus.
For the Pentium 4 and Intel Xeonprocessors, the xAPIC specification extends the local APIC ID field to 8 bits. Thesecan be used to identify up to 255 processors in the system.8.4.7Local APIC StateThe following sections describe the state of the local APIC and its registers followinga power-up or RESET, after the local APIC has been software disabled, following anINIT reset, and following an INIT-deassert message.8.4.7.1Local APIC State After Power-Up or ResetFollowing a power-up or RESET of the processor, the state of local APIC and its registers are as follows:•The following registers are reset to all 0s:•••••••IRR, ISR, TMR, ICR, LDR, and TPRTimer initial count and timer current count registersDivide configuration registerThe DFR register is reset to all 1s.The LVT register is reset to 0s except for the mask bits; these are set to 1s.The local APIC version register is not affected.The local APIC ID register is set to a unique APIC ID.
(Pentium and P6 familyprocessors only). The Arb ID register is set to the value in the APIC ID register.Vol. 3 8-13ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)•The spurious-interrupt vector register is initialized to 000000FFH. By setting bit 8to 0, software disables the local APIC.•If the processor is the only processor in the system or it is the BSP in an MPsystem (see Section 7.5.1, “BSP and AP Processors”); the local APIC will respondnormally to INIT and NMI messages, to INIT# signals and to STPCLK# signals. Ifthe processor is in an MP system and has been designated as an AP; the localAPIC will respond the same as for the BSP. In addition, it will respond to SIPImessages.
For P6 family processors only, an AP will not respond to a STPCLK#signal.8.4.7.2Local APIC State After It Has Been Software DisabledWhen the APIC software enable/disable flag in the spurious interrupt vector registerhas been explicitly cleared (as opposed to being cleared during a power up orRESET), the local APIC is temporarily disabled (see Section 8.4.3, “Enabling orDisabling the Local APIC”). The operation and response of a local APIC while in thissoftware-disabled state is as follows:••The local APIC will respond normally to INIT, NMI, SMI, and SIPI messages.•The local APIC can still issue IPIs. It is software’s responsibility to avoid issuingIPIs through the IPI mechanism and the ICR register if sending interruptsthrough this mechanism is not desired.•The reception or transmission of any IPIs that are in progress when the local APICis disabled are completed before the local APIC enters the software-disabledstate.•The mask bits for all the LVT entries are set.
Attempts to reset these bits will beignored.•(For Pentium and P6 family processors) The local APIC continues to listen to allbus messages in order to keep its arbitration ID synchronized with the rest of thesystem.Pending interrupts in the IRR and ISR registers are held and require masking orhandling by the CPU.8.4.7.3Local APIC State After an INIT Reset (“Wait-for-SIPI” State)An INIT reset of the processor can be initiated in either of two ways:••By asserting the processor’s INIT# pin.By sending the processor an INIT IPI (an IPI with the delivery mode set to INIT).Upon receiving an INIT through either of these mechanisms, the processor respondsby beginning the initialization process of the processor core and the local APIC.
Thestate of the local APIC following an INIT reset is the same as it is after a power-up orhardware RESET, except that the APIC ID and arbitration ID registers are notaffected. This state is also referred to at the “wait-for-SIPI” state (see also: Section8-14 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)7.5.2, “MP Initialization Protocol Requirements and Restrictions for Intel XeonProcessors”).8.4.7.4Local APIC State After It Receives an INIT-Deassert IPIOnly the Pentium and P6 family processors support the INIT-deassert IPI.
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