Volume 3A System Programming Guide_ Part 1 (794103), страница 84
Текст из файла (страница 84)
An INITdisassert IPI has no affect on the state of the APIC, other than to reload the arbitration ID register with the value in the APIC ID register.8.4.8Local APIC Version RegisterThe local APIC contains a hardwired version register. Software can use this register toidentify the APIC version (see Figure 8-7). In addition, the register specifies thenumber of entries in the local vector table (LVT) for a specific implementation.The fields in the local APIC version register are as follows:VersionThe version numbers of the local APIC:Max LVT Entry1XHLocal APIC. For Pentium 4 and Intel Xeonprocessors, 14H is returned.0XH82489DX external APIC.20H - FFHReserved.Shows the number of LVT entries minus 1.
For the Pentium 4 andIntel Xeon processors (which have 6 LVT entries), the valuereturned in the Max LVT field is 5; for the P6 family processors(which have 5 LVT entries), the value returned is 4; for thePentium processor (which has 4 LVT entries), the value returnedis 3.3124 23Reserved16 15Max. LVTEntry08 7ReservedVersionValue after reset: 000N 00VVHV = Version, N = # of LVT entries minus 1Address: FEE0 0030HFigure 8-7. Local APIC Version Register8.5HANDLING LOCAL INTERRUPTSThe following sections describe facilities that are provided in the local APIC forhandling local interrupts.
These include: the processor’s LINT0 and LINT1 pins, theAPIC timer, the performance-monitoring counters, the thermal sensor, and theVol. 3 8-15ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)internal APIC error detector. Local interrupt handling facilities include: the LVT, theerror status register (ESR), the divide configuration register (DCR), and the initialcount and current count registers.8.5.1Local Vector TableThe local vector table (LVT) allows software to specify the manner in which the localinterrupts are delivered to the processor core. It consists of the following five 32-bitAPIC registers (see Figure 8-8), one for each local interrupt:•LVT Timer Register (FEE0 0320H) — Specifies interrupt delivery when theAPIC timer signals an interrupt (see Section 8.5.4, “APIC Timer”).•LVT Thermal Monitor Register (FEE0 0330H) — Specifies interrupt deliverywhen the thermal sensor generates an interrupt (see Section 13.5.2, “ThermalMonitor”).
This LVT entry is implementation specific, not architectural. If implemented, it will always be at base address FEE0 0330H.•LVT Performance Counter Register (FEE0 0340H) — Specifies interruptdelivery when a performance counter generates an interrupt on overflow (seeSection 18.15.6.8, “Generating an Interrupt on Overflow”). This LVT entry isimplementation specific, not architectural. If implemented, it is not guaranteedto be at base address FEE0 0340H.•LVT LINT0 Register (FEE0 0350H) — Specifies interrupt delivery when aninterrupt is signaled at the LINT0 pin.•LVT LINT1 Register (FEE0 0360H) — Specifies interrupt delivery when aninterrupt is signaled at the LINT1 pin.•LVT Error Register (FEE0 0370H) — Specifies interrupt delivery when theAPIC detects an internal error (see Section 8.5.3, “Error Handling”).The LVT performance counter register and its associated interrupt were introduced inthe P6 processors and are also present in the Pentium 4 and Intel Xeon processors.The LVT thermal monitor register and its associated interrupt were introduced in thePentium 4 and Intel Xeon processors.As shown in Figures 8-8, some of these fields and flags are not available (andreserved) for some entries.8-16 Vol.
3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)3118 17 16 1513 12 118 70TimerVectorAddress: FEE0 0320HValue after Reset: 0001 0000HTimer Mode0: One-shot1: PeriodicDelivery Status0: Idle1: Send PendingMask†0: Not Masked1: MaskedInterrupt InputPin PolarityDelivery Mode000: Fixed010: SMI100: NMI111: ExtlNT101: INITAll other combinationsare ReservedRemoteIRRTrigger Mode0: Edge1: Level311711 108 70LINT0VectorLINT1VectorErrorVectorPerformanceMon. CountersVectorThermalSensorVector161514 13 12Reserved† (Pentium 4 and Intel Xeon processors.) When aperformance monitoring counters interrupt is generated,the mask bit for its associated LVT entry is set.Address: FEE0 0350HAddress: FEE0 0360HAddress: FEE0 0370HAddress: FEE0 0340HAddress: FEE0 0330HValue After Reset: 0001 0000HFigure 8-8. Local Vector Table (LVT)Vol.
3 8-17ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)The setup information that can be specified in the registers of the LVT table is asfollows:VectorInterrupt vector number.Delivery ModeSpecifies the type of interrupt to be sent to the processor. Somedelivery modes will only operate as intended when used inconjunction with a specific trigger mode.
The allowable deliverymodes are as follows:000 (Fixed)Delivers the interrupt specified in the vectorfield.010 (SMI)Delivers an SMI interrupt to the processorcore through the processor’s local SMI signalpath. When using this delivery mode, thevector field should be set to 00H for futurecompatibility.100 (NMI)Delivers an NMI interrupt to the processor.The vector information is ignored.101 (INIT)Delivers an INIT request to the processorcore, which causes the processor to performan INIT. When using this delivery mode, thevector field should be set to 00H for futurecompatibility.111 (ExtINT) Causes the processor to respond to the interrupt as if the interrupt originated in anexternally connected (8259A-compatible)interrupt controller. A special INTA bus cyclecorresponding to ExtINT, is routed to the external controller.
The external controller isexpected to supply the vector information.The APIC architecture supports only one ExtINT source in a system, usually contained inthe compatibility bridge.Delivery Status (Read Only)Indicates the interrupt delivery status, as follows:0 (Idle)There is currently no activity for this interrupt source, or the previous interrupt fromthis source was delivered to the processorcore and accepted.1 (Send Pending)Indicates that an interrupt from this sourcehas been delivered to the processor core,but has not yet been accepted (see Section8.5.5, “Local Interrupt Acceptance”).Interrupt Input Pin PolaritySpecifies the polarity of the corresponding interrupt pin: (0)active high or (1) active low.8-18 Vol.
3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Remote IRR Flag (Read Only)For fixed mode, level-triggered interrupts; this flag is set whenthe local APIC accepts the interrupt for servicing and is resetwhen an EOI command is received from the processor. Themeaning of this flag is undefined for edge-triggered interruptsand other delivery modes.Trigger ModeSelects the trigger mode for the local LINT0 and LINT1 pins: (0)edge sensitive and (1) level sensitive.
This flag is only usedwhen the delivery mode is Fixed. When the delivery mode isNMI, SMI, or INIT, the trigger mode is always edge sensitive.When the delivery mode is ExtINT, the trigger mode is alwayslevel sensitive. The timer and error interrupts are always treatedas edge sensitive.If the local APIC is not used in conjunction with an I/O APIC andfixed delivery mode is selected; the Pentium 4, Intel Xeon, andP6 family processors will always use level-sensitive triggering,regardless if edge-sensitive triggering is selected.MaskInterrupt mask: (0) enables reception of the interrupt and (1)inhibits reception of the interrupt. When the local APIC handlesa performance-monitoring counters interrupt, it automaticallysets the mask flag in the corresponding LVT entry. This flag willremain set until software clears it.Timer ModeSelects the timer mode: (0) one-shot and (1) periodic (seeSection 8.5.4, “APIC Timer”).8.5.2Valid Interrupt VectorsThe Intel 64 and IA-32 architectures define 256 vector numbers, ranging from 0through 255 (see Section 5.2, “Exception and Interrupt Vectors”).
Local and I/OAPICs support 240 of these vectors (in the range of 16 to 255) as valid interrupts.When an interrupt vector in the range of 0 to 15 is sent or received through the localAPIC, the APIC indicates an illegal vector in its Error Status Register (see Section8.5.3, “Error Handling”). The Intel 64 and IA-32 architectures reserve vectors 16through 31 for predefined interrupts, exceptions, and Intel-reserved encodings (seeTable 5-1). However, the local APIC does not treat vectors in this range as illegal.When an illegal vector value (0 to 15) is written to an LVT entry and the deliverymode is Fixed (bits 8-11 equal 0), the APIC may signal an illegal vector error, withoutregard to whether the mask bit is set or whether an interrupt is actually seen on theinput.8.5.3Error HandlingThe local APIC provides an error status register (ESR) that it uses to record errorsthat it detects when handling interrupts (see Figure 8-9).
An APIC error interrupt isVol. 3 8-19ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)generated when the local APIC sets one of the error bits in the ESR. The LVT errorregister allows selection of the interrupt vector to be delivered to the processor corewhen APIC error is detected. The LVT error register also provides a means of maskingan APIC error interrupt.The functions of the ESR are listed in Table 8-2.Table 8-2. ESR FlagsFLAGFunctionSend Checksum Error(P6 family and Pentium processors only) Set when the local APICdetects a checksum error for a message that it sent on the APIC bus.Receive Checksum Error(P6 family and Pentium processors only) Set when the local APICdetects a checksum error for a message that it received on the APICbus.Send Accept Error(P6 family and Pentium processors only) Set when the local APICdetects that a message it sent was not accepted by any APIC on theAPIC bus.Receive Accept Error(P6 family and Pentium processors only) Set when the local APICdetects that the message it received was not accepted by any APICon the APIC bus, including itself.Send Illegal VectorSet when the local APIC detects an illegal vector in the message thatit is sending.Receive Illegal VectorSet when the local APIC detects an illegal vector in the message itreceived, including an illegal vector code in the local vector tableinterrupts or in a self-interrupt.Illegal Reg.
Address(Pentium 4, Intel Xeon, and P6 family processors only) Set when theprocessor is trying to access a register in the processor's local APICregister address space that is reserved (see Table 8-1). Addresses inone the 0x10 byte regions marked reserved are illegal registeraddresses.The Local APIC Register Map is the address range of the APICregister base address (specified in the IA32_APIC_BASE MSR) plus4 KBytes.8-20 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)8 7 6 5 4 3 2 1 031ReservedIllegal Register Address1Received Illegal VectorSend Illegal VectorReservedReceive Accept Error2Send Accept Error2Receive Checksum Error2Send Checksum Error2Address: FEE0 0280HValue after reset: 0HNOTES:1.
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