Volume 3A System Programming Guide_ Part 1 (794103), страница 85
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Only used in the Pentium 4, Intel Xeon, and P6 familyprocessors; reserved in the Pentium processor.2. Only used in the P6 family and Pentium processors;reserved in the Pentium 4 and Intel Xeon processors.Figure 8-9. Error Status Register (ESR)The ESR is a write/read register. A write (of any value) to the ESR must be done justprior to reading the ESR to update the register. This initial write causes the ESRcontents to be updated with the latest error status. Back-to-back writes clear the ESRregister.After an error bit is set in the register, it remains set until the register is cleared.Setting the mask bit for the LVT error register prevents errors from being recorded inthe ESR; however, the state of the ESR before the mask bit was set is maintained.8.5.4APIC TimerThe local APIC unit contains a 32-bit programmable timer that is available to software to time events or operations.
This timer is set up by programming four registers: the divide configuration register (see Figure 8-10), the initial-count andcurrent-count registers (see Figure 8-11), and the LVT timer register (seeFigure 8-8).NOTEThe APIC timer may temporarily stop while the processor is in deepC-states or during transitions caused by Enhanced Intel SpeedStep®Technology.Vol. 3 8-21ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)4 3 2 1 031ReservedAddress: FEE0 03E0HValue after reset: 0H0Divide Value (bits 0, 1 and 3)000: Divide by 2001: Divide by 4010: Divide by 8011: Divide by 16100: Divide by 32101: Divide by 64110: Divide by 128111: Divide by 1Figure 8-10. Divide Configuration Register310Initial CountCurrent CountAddress: Initial Count FEE0 0380HCurrent Count FEE0 0390HValue after reset: 0HFigure 8-11. Initial Count and Current Count RegistersThe time base for the timer is derived from the processor’s bus clock, divided by thevalue specified in the divide configuration register.The timer can be configured through the timer LVT entry for one-shot or periodicoperation.
In one-shot mode, the timer is started by programming its initial-countregister. The initial count value is then copied into the current-count register andcount-down begins. After the timer reaches zero, an timer interrupt is generated andthe timer remains at its 0 value until reprogrammed.In periodic mode, the current-count register is automatically reloaded from theinitial-count register when the count reaches 0 and a timer interrupt is generated,and the count-down is repeated. If during the count-down process the initial-countregister is set, counting will restart, using the new initial-count value.
The initialcount register is a read-write register; the current-count register is read only.The LVT timer register determines the vector number that is delivered to theprocessor with the timer interrupt that is generated when the timer count reacheszero. The mask flag in the LVT timer register can be used to mask the timer interrupt.8-22 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)8.5.5Local Interrupt AcceptanceWhen a local interrupt is sent to the processor core, it is subject to the acceptancecriteria specified in the interrupt acceptance flow chart in Figure 8-17.
If the interruptis accepted, it is logged into the IRR register and handled by the processor accordingto its priority (see Section 8.8.4, “Interrupt Acceptance for Fixed Interrupts”). If theinterrupt is not accepted, it is sent back to the local APIC and retried.8.6ISSUING INTERPROCESSOR INTERRUPTSThe following sections describe the local APIC facilities that are provided for issuinginterprocessor interrupts (IPIs) from software. The primary local APIC facility forissuing IPIs is the interrupt command register (ICR). The ICR can be used for thefollowing functions:••To send an interrupt to another processor.••To direct the processor to interrupt itself (perform a self interrupt).To allow a processor to forward an interrupt that it received but did not service toanother processor for servicing.To deliver special IPIs, such as the start-up IPI (SIPI) message, to otherprocessors.Interrupts generated with this facility are delivered to the other processors in thesystem through the system bus (for Pentium 4 and Intel Xeon processors) or theAPIC bus (for P6 family and Pentium processors).
The ability for a processor to senda lowest priority IPI is model specific and should be avoided by BIOS and operatingsystem software.8.6.1Interrupt Command Register (ICR)The interrupt command register (ICR) is a 64-bit local APIC register (seeFigure 8-12) that allows software running on the processor to specify and send interprocessor interrupts (IPIs) to other processors in the system.To send an IPI, software must set up the ICR to indicate the type of IPI message tobe sent and the destination processor or processors.
(All fields of the ICR are readwrite by software with the exception of the delivery status field, which is read-only.)The act of writing to the low doubleword of the ICR causes the IPI to be sent.Vol. 3 8-23ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)6356 5532Destination FieldReserved3120 19 18 17 16 15 14 13 12 11 10ReservedDestination Shorthand00: No Shorthand01: Self10: All Including Self11: All Excluding SelfReserved8 70VectorDelivery Mode000: Fixed001: Lowest Priority1010: SMI011: Reserved100: NMI101: INIT110: Start Up111: ReservedDestination Mode0: Physical1: LogicalDelivery Status0: Idle1: Send PendingAddress: FEE0 0300H (0 - 31)FEE0 0310H (32 - 63)Value after Reset: 0HLevel0 = De-assert1 = AssertTrigger Mode0: Edge1: LevelNOTE:1.
The ability of a processor to send Lowest Priority IPI is model specific.Figure 8-12. Interrupt Command Register (ICR)The ICR consists of the following fields.VectorThe vector number of the interrupt being sent.Delivery ModeSpecifies the type of IPI to be sent. This field is also know as theIPI message type field.000 (Fixed)Delivers the interrupt specified in the vectorfield to the target processor or processors.001 (Lowest Priority)Same as fixed mode, except that the interrupt is delivered to the processor executingat the lowest priority among the set of processors specified in the destination field. The8-24 Vol.
3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)ability for a processor to send a lowest priority IPI is model specific and should be avoided by BIOS and operating system software.010 (SMI)Delivers an SMI interrupt to the target processor or processors. The vector field mustbe programmed to 00H for future compatibility.011 (Reserved)100 (NMI)Delivers an NMI interrupt to the target processor or processors. The vector informationis ignored.101 (INIT)Delivers an INIT request to the target processor or processors, which causes them toperform an INIT.
As a result of this IPI message, all the target processors perform anINIT. The vector field must be programmedto 00H for future compatibility.101 (INIT Level De-assert)(Not supported in the Pentium 4 and IntelXeon processors.) Sends a synchronizationmessage to all the local APICs in the systemto set their arbitration IDs (stored in theirArb ID registers) to the values of their APICIDs (see Section 8.7, “System and APIC BusArbitration”).
For this delivery mode, thelevel flag must be set to 0 and trigger modeflag to 1. This IPI is sent to all processors,regardless of the value in the destinationfield or the destination shorthand field; however, software should specify the “all including self” shorthand.110 (Start-Up)Sends a special “start-up” IPI (called a SIPI)to the target processor or processors. Thevector typically points to a start-up routinethat is part of the BIOS boot-strap code (seeSection 7.5, “Multiple-Processor (MP) Initialization”). IPIs sent with this delivery modeare not automatically retried if the sourceAPIC is unable to deliver it.
It is up to thesoftware to determine if the SIPI was notsuccessfully delivered and to reissue theSIPI if necessary.Vol. 3 8-25ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Destination Mode Selects either physical (0) or logical (1) destination mode (seeSection 8.6.2, “Determining IPI Destination”).Delivery Status (Read Only)Indicates the IPI delivery status, as follows:0 (Idle)There is currently no IPI activity for this localAPIC, or the previous IPI sent from this localAPIC was delivered and accepted by the target processor or processors.1 (Send Pending)Indicates that the last IPI sent from this local APIC has not yet been accepted by thetarget processor or processors.LevelFor the INIT level de-assert delivery mode this flag must be setto 0; for all other delivery modes it must be set to 1.
(This flaghas no meaning in Pentium 4 and Intel Xeon processors, and willalways be issued as a 1.)Trigger ModeSelects the trigger mode when using the INIT level de-assertdelivery mode: edge (0) or level (1). It is ignored for all otherdelivery modes. (This flag has no meaning in Pentium 4 andIntel Xeon processors, and will always be issued as a 0.)Destination ShorthandIndicates whether a shorthand notation is used to specify thedestination of the interrupt and, if so, which shorthand is used.Destination shorthands are used in place of the 8-bit destinationfield, and can be sent by software using a single write to the lowdoubleword of the ICR.
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