Volume 3A System Programming Guide_ Part 1 (794103), страница 87
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Agroup of local APICs can then be selected by setting one or more bits in the MDA.Each local APIC performs a bit-wise AND of the MDA and its logical APIC ID. If atrue condition is detected, the local APIC accepts the IPI message. A broadcast toall APICs is achieved by setting the MDA to 1s.2. Cluster Model — This model is selected by programming DFR bits 28 through 31to 0000. This model supports two basic destination schemes: flat cluster andhierarchical cluster.The flat cluster destination model is only supported for P6 family and Pentiumprocessors.
Using this model, all APICs are assumed to be connected through theVol. 3 8-31ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)APIC bus. Bits 28 through 31 of the MDA contains the encoded address of thedestination cluster and bits 24 through 27 identify up to four local APICs withinthe cluster (each bit is assigned to one local APIC in the cluster, as in the flatconnection model). To identify one or more local APICs, bits 28 through 31 of theMDA are compared with bits 28 through 31 of the LDR to determine if a local APICis part of the cluster. Bits 24 through 27 of the MDA are compared with Bits 24through 27 of the LDR to identify a local APICs within the cluster.Sets of processors within a cluster can be specified by writing the target clusteraddress in bits 28 through 31 of the MDA and setting selected bits in bits 24through 27 of the MDA, corresponding to the chosen members of the cluster.
Inthis mode, 15 clusters (with cluster addresses of 0 through 14) each having 4local APICs can be specified in the message. For the P6 and Pentium processor’slocal APICs, however, the APIC arbitration ID supports only 15 APIC agents.Therefore, the total number of processors and their local APICs supported inthis mode is limited to 15. Broadcast to all local APICs is achieved by setting alldestination bits to one. This guarantees a match on all clusters and selects allAPICs in each cluster.
A broadcast IPI or I/O subsystem broadcast interrupt withlowest priority delivery mode is not supported in cluster mode and must not beconfigured by software.The hierarchical cluster destination model can be used with Pentium 4, IntelXeon, P6 family, or Pentium processors. With this model, a hierarchical networkcan be created by connecting different flat clusters via independent system orAPIC buses. This scheme requires a cluster manager within each cluster, which isresponsible for handling message passing between system or APIC buses.
Onecluster contains up to 4 agents. Thus 15 cluster managers, each with 4 agents,can form a network of up to 60 APIC agents. Note that hierarchical APIC networksrequires a special cluster manager device, which is not part of the local or the I/OAPIC units.NOTESAll processors that have their APIC software enabled (using thespurious vector enable/disable bit) must have their DFRs (Destination Format Registers) programmed identically.The default mode for DFR is flat mode. If you are using cluster mode,DFRs must be programmed before the APIC is software enabled.Since some chipsets do not accurately track a system view of thelogical mode, program DFRs as soon as possible after starting theprocessor.8.6.2.3Broadcast/Self Delivery ModeThe destination shorthand field of the ICR allows the delivery mode to be by-passedin favor of broadcasting the IPI to all the processors on the system bus and/or backto itself (see Section 8.6.1, “Interrupt Command Register (ICR)”).
Three destination8-32 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)shorthands are supported: self, all excluding self, and all including self. The destination mode is ignored when a destination shorthand is used.8.6.2.4Lowest Priority Delivery ModeWith lowest priority delivery mode, the ICR is programmed to send an IPI to severalprocessors on the system bus, using the logical or shorthand destination mechanismfor selecting the processor. The selected processors then arbitrate with one anotherover the system bus or the APIC bus, with the lowest-priority processor accepting theIPI.For systems based on the Intel Xeon processor, the chipset bus controller acceptsmessages from the I/O APIC agents in the system and directs interrupts to theprocessors on the system bus.
When using the lowest priority delivery mode, thechipset chooses a target processor to receive the interrupt out of the set of possibletargets. The Pentium 4 processor provides a special bus cycle on the system bus thatinforms the chipset of the current task priority for each logical processor in thesystem. The chipset saves this information and uses it to choose the lowest priorityprocessor when an interrupt is received.For systems based on P6 family processors, the processor priority used in lowestpriority arbitration is contained in the arbitration priority register (APR) in each localAPIC. Figure 8-15 shows the layout of the APR.318 74 30ReservedAddress: FEE0 0090HValue after reset: 0HArbitration PriorityArbitration Priority Sub-ClassFigure 8-15.
Arbitration Priority Register (APR)The APR value is computed as follows:IF (TPR[7:4] ≥ IRRV[7:4]) AND (TPR[7:4] > ISRV[7:4])THENAPR[7:0] ← TPR[7:0]ELSEAPR[7:4] ← max(TPR[7:4] AND ISRV[7:4], IRRV[7:4])APR[3:0] ← 0.Here, the TPR value is the task priority value in the TPR (see Figure 8-18), the IRRVvalue is the vector number for the highest priority bit that is set in the IRR (seeFigure 8-20) or 00H (if no IRR bit is set), and the ISRV value is the vector number forthe highest priority bit that is set in the ISR (see Figure 8-20).
Following arbitrationVol. 3 8-33ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)among the destination processors, the processor with the lowest value in its APRhandles the IPI and the other processors ignore it.(P6 family and Pentium processors.) For these processors, if a focus processorexists, it may accept the interrupt, regardless of its priority. A processor is said to bethe focus of an interrupt if it is currently servicing that interrupt or if it has a pendingrequest for that interrupt. For Intel Xeon processors, the concept of a focus processoris not supported.In operating systems that use the lowest priority delivery mode but do not updatethe TPR, the TPR information saved in the chipset will potentially cause the interruptto be always delivered to the same processor from the logical set.
This behavior isfunctionally backward compatible with the P6 family processor but may result inunexpected performance implications.8.6.3IPI Delivery and AcceptanceWhen the low double-word of the ICR is written to, the local APIC creates an IPImessage from the information contained in the ICR and sends the message out onthe system bus (Pentium 4 and Intel Xeon processors) or the APIC bus (P6 family andPentium processors). The manner in which these IPIs are handled after being issuesin described in Section 8.8, “Handling Interrupts.”8.7SYSTEM AND APIC BUS ARBITRATIONWhen several local APICs and the I/O APIC are sending IPI and interrupt messageson the system bus (or APIC bus), the order in which the messages are sent andhandled is determined through bus arbitration.For the Pentium 4 and Intel Xeon processors, the local and I/O APICs use the arbitration mechanism defined for the system bus to determine the order in which IPIs arehandled.
This mechanism is non-architectural and cannot be controlled by software.For the P6 family and Pentium processors, the local and I/O APICs use an APIC-basedarbitration mechanism to determine the order in which IPIs are handled. Here, eachlocal APIC is given an arbitration priority of from 0 to 15, which the I/O APIC usesduring arbitration to determine which local APIC should be given access to the APICbus.
The local APIC with the highest arbitration priority always wins bus access. Uponcompletion of an arbitration round, the winning local APIC lowers its arbitrationpriority to 0 and the losing local APICs each raise theirs by 1.The current arbitration priority for a local APIC is stored in a 4-bit, software-transparent arbitration ID (Arb ID) register. During reset, this register is initialized to theAPIC ID number (stored in the local APIC ID register). The INIT level-deassert IPI,which is issued with and ICR command, can be used to resynchronize the arbitrationpriorities of the local APICs by resetting Arb ID register of each agent to its currentAPIC ID value.
(The Pentium 4 and Intel Xeon processors do not implement the ArbID register.)8-34 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Section 8.10, “APIC Bus Message Passing Mechanism and Protocol (P6 Family,Pentium Processors),” describes the APIC bus arbitration protocols and bus messageformats, while Section 8.6.1, “Interrupt Command Register (ICR),” describes theINIT level de-assert IPI message.Note that except for the SIPI IPI (see Section 8.6.1, “Interrupt Command Register(ICR)”), all bus messages that fail to be delivered to their specified destination ordestinations are automatically retried. Software should avoid situations in which IPIsare sent to disabled or nonexistent local APICs, causing the messages to be resentrepeatedly.8.8HANDLING INTERRUPTSWhen a local APIC receives an interrupt from a local source, an interrupt messagefrom an I/O APIC, or and IPI, the manner in which it handles the message dependson processor implementation, as described in the following sections.8.8.1Interrupt Handling with the Pentium 4 and Intel XeonProcessorsWith the Pentium 4 and Intel Xeon processors, the local APIC handles the local interrupts, interrupt messages, and IPIs it receives as follows:1.
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