Volume 3A System Programming Guide_ Part 1 (794103), страница 88
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It determines if it is the specified destination or not (see Figure 8-16). If it is thespecified destination, it accepts the message; if it is not, it discards the message.Wait to ReceiveBus MessageDiscardMessageNoBelong toDestination?YesAcceptMessageFigure 8-16. Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and IntelXeon Processors)2. If the local APIC determines that it is the designated destination for the interruptand if the interrupt request is an NMI, SMI, INIT, ExtINT, or SIPI, the interrupt issent directly to the processor core for handling.3.
If the local APIC determines that it is the designated destination for the interruptbut the interrupt request is not one of the interrupts given in step 2, the localAPIC sets the appropriate bit in the IRR.Vol. 3 8-35ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)4. When interrupts are pending in the IRR and ISR register, the local APICdispatches them to the processor one at a time, based on their priority and thecurrent task and processor priorities in the TPR and PPR (see Section 8.8.3.1,“Task and Processor Priorities”).5.
When a fixed interrupt has been dispatched to the processor core for handling,the completion of the handler routine is indicated with an instruction in theinstruction handler code that writes to the end-of-interrupt (EOI) register in thelocal APIC (see Section 8.8.5, “Signaling Interrupt Servicing Completion”). Theact of writing to the EOI register causes the local APIC to delete the interruptfrom its ISR queue and (for level-triggered interrupts) send a message on thebus indicating that the interrupt handling has been completed. (A write to the EOIregister must not be included in the handler routine for an NMI, SMI, INIT,ExtINT, or SIPI.)8.8.2Interrupt Handling with the P6 Family and PentiumProcessorsWith the P6 family and Pentium processors, the local APIC handles the local interrupts, interrupt messages, and IPIs it receives as follows (see Figure 8-17).8-36 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Wait to ReceiveBus MessageNoDiscardMessageBelongtoDestination?YesIs itNMI/SMI/INIT/ExtINT?YesAcceptMessageNoFixedDeliveryLowesPriorityP6 FamilyProcessor SpecificNoSet Statusto RetryAm IFocus?Is Interrupt SlotAvailable?YesYesIs Status aRetry?YesAcceptMessageYesDiscardMessageNoNoOtherFocus?NoSet Statusto RetryNoAcceptMessageIs InterruptSlot Available?YesNoArbitrateAm I Winner?YesAcceptMessageFigure 8-17.
Interrupt Acceptance Flow Chart for the Local APIC (P6 Family andPentium Processors)1. (IPIs only) It examines the IPI message to determines if it is the specifieddestination for the IPI as described in Section 8.6.2, “Determining IPI Destination.” If it is the specified destination, it continues its acceptance procedure; ifit is not the destination, it discards the IPI message.
When the message specifieslowest-priority delivery mode, the local APIC will arbitrate with the otherprocessors that were designated on recipients of the IPI message (see Section8.6.2.4, “Lowest Priority Delivery Mode”).2. If the local APIC determines that it is the designated destination for the interruptand if the interrupt request is an NMI, SMI, INIT, ExtINT, or INIT-deassertVol. 3 8-37ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)interrupt, or one of the MP protocol IPI messages (BIPI, FIPI, and SIPI), theinterrupt is sent directly to the processor core for handling.3.
If the local APIC determines that it is the designated destination for the interruptbut the interrupt request is not one of the interrupts given in step 2, the localAPIC looks for an open slot in one of its two pending interrupt queues containedin the IRR and ISR registers (see Figure 8-20). If a slot is available (see Section8.8.4, “Interrupt Acceptance for Fixed Interrupts”), places the interrupt in theslot.
If a slot is not available, it rejects the interrupt request and sends it back tothe sender with a retry message.4. When interrupts are pending in the IRR and ISR register, the local APICdispatches them to the processor one at a time, based on their priority and thecurrent task and processor priorities in the TPR and PPR (see Section 8.8.3.1,“Task and Processor Priorities”).5. When a fixed interrupt has been dispatched to the processor core for handling,the completion of the handler routine is indicated with an instruction in theinstruction handler code that writes to the end-of-interrupt (EOI) register in thelocal APIC (see Section 8.8.5, “Signaling Interrupt Servicing Completion”). Theact of writing to the EOI register causes the local APIC to delete the interruptfrom its queue and (for level-triggered interrupts) send a message on the busindicating that the interrupt handling has been completed.
(A write to the EOIregister must not be included in the handler routine for an NMI, SMI, INIT,ExtINT, or SIPI.)The following sections describe the acceptance of interrupts and their handling by thelocal APIC and processor in greater detail.8.8.3Interrupt, Task, and Processor PriorityFor interrupts that are delivered to the processor through the local APIC, each interrupt has an implied priority based on its vector number. The local APIC uses thispriority to determine when to service the interrupt relative to the other activities ofthe processor, including the servicing of other interrupts.For interrupt vectors in the range of 16 to 255, the interrupt priority is determinedusing the following relationship:priority = vector / 16Here the quotient is rounded down to the nearest integer value to determine thepriority, with 1 being the lowest priority and 15 is the highest.
Because vectors 0through 31 are reserved for dedicated uses by the Intel 64 and IA-32 architectures,the priorities of user defined interrupts range from 2 to 15.Each interrupt priority level (sometimes interpreted by software as an interruptpriority class) encompasses 16 vectors. Prioritizing interrupts within a priority level isdetermined by the vector number. The higher the vector number, the higher thepriority within that priority level. In determining the priority of a vector and ranking8-38 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)of vectors within a priority group, the vector number is often divided into two parts,with the high 4 bits of the vector indicating its priority and the low 4 bit indicating itsranking within the priority group.8.8.3.1Task and Processor PrioritiesThe local APIC also defines a task priority and a processor priority that it uses indetermining the order in which interrupts should be handled.
The task priority is asoftware selected value between 0 and 15 (see Figure 8-18) that is written into thetask priority register (TPR). The TPR is a read/write register.318 74 30ReservedAddress: FEE0 0080HValue after reset: 0HTask PriorityTask Priority Sub-ClassFigure 8-18. Task Priority Register (TPR)NOTEIn this discussion, the term “task” refers to a software defined task,process, thread, program, or routine that is dispatched to run on theprocessor by the operating system.
It does not refer an IA-32 architecture defined task as described in Chapter 6, “Task Management.”The task priority allows software to set a priority threshold for interrupting theprocessor. The processor will service only those interrupts that have a priority higherthan that specified in the TPR. If software sets the task priority in the TPR to 0, theprocessor will handle all interrupts; it is it set to 15, all interrupts are inhibited frombeing handled, except those delivered with the NMI, SMI, INIT, ExtINT, INIT-deassert, and start-up delivery mode.
This mechanism enables the operating system totemporarily block specific interrupts (generally low priority interrupts) fromdisturbing high-priority work that the processor is doing.Note that the task priority is also used to determine the arbitration priority of thelocal processor (see Section 8.6.2.4, “Lowest Priority Delivery Mode”).The processor priority is set by the processor, also to value between 0 and 15 (seeFigure 8-19) that is written into the processor priority register (PPR).
The PPR is aread only register. The processor priority represents the current priority at which theprocessor is executing. It is used to determine whether a pending interrupt can bedispensed to the processor.Vol. 3 8-39ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)318 74 30ReservedAddress: FEE0 00A0HValue after reset: 0HProcessor PriorityProcessor Priority Sub-ClassFigure 8-19.
Processor Priority Register (PPR)Its value in the PPR is computed as follows:IF TPR[7:4] ≥ ISRV[7:4]THENPPR[7:0] ← TPR[7:0]ELSEPPR[7:4] ← ISRV[7:4]PPR[3:0] ← 0Here, the ISRV value is the vector number of the highest priority ISR bit that is set,or 00H if no ISR bit is set. Essentially, the processor priority is set to either to thehighest priority pending interrupt in the ISR or to the current task priority, whicheveris higher.8.8.4Interrupt Acceptance for Fixed InterruptsThe local APIC queues the fixed interrupts that it accepts in one of two interruptpending registers: the interrupt request register (IRR) or in-service register (ISR).These two 256-bit read-only registers are shown in Figure 8-20.
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