Volume 3A System Programming Guide_ Part 1 (794103), страница 92
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The 10 most-significant bits of the EFLAGS register are undefined following a reset. Softwareshould not depend on the states of any of these bits.2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared.3. Where “n” is the Extended Model Value for the respective processor.4. If Built-In Self-Test (BIST) is invoked on power up or reset, EAX is 0 only if all tests passed.
(BISTcannot be invoked during an INIT.)5. The state of the x87 FPU and MMX registers is not changed by the execution of an INIT.9-4 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONPaging disabled: 0Caching disabled: 1Not write-through disabled: 1Alignment check disabled: 0Write-protect disabled: 031 30 29 28P C NGDW19 18 17 16 15ReservedAM6 5 4 3 2 1 0WPNT E M P1ES MP EReservedExternal x87 FPU error reporting: 0(Not used): 1No task switch: 0x87 FPU instructions not trapped: 0WAIT/FWAIT instructions not trapped: 0Real-address mode: 0Figure 9-1.
Contents of CR0 Register after Reset9.1.3Model and Stepping InformationFollowing a hardware reset, the EDX register contains component identification andrevision information (see Figure 9-2). For example, the model, family, and processortype returned for the first processor in the Intel Pentium 4 family is as follows: model(0000B), family (1111B), and processor type (00B).31EAX24 2320 19ExtendedFamily16 15 14 13 12 11ExtendedModelFamily8 74 3Model0SteppingIDProcessor TypeFamily (1111B for the Pentium 4 Processor Family)Model (Beginning with 0000B)ReservedFigure 9-2.
Version Information in the EDX Register after ResetThe stepping ID field contains a unique identifier for the processor’s stepping ID orrevision level. The extended family and extended model fields were added to theIA-32 architecture in the Pentium 4 processors.Vol. 3 9-5PROCESSOR MANAGEMENT AND INITIALIZATION9.1.4First Instruction ExecutedThe first instruction that is fetched and executed following a hardware reset islocated at physical address FFFFFFF0H. This address is 16 bytes below theprocessor’s uppermost physical address.
The EPROM containing the softwareinitialization code must be located at this address.The address FFFFFFF0H is beyond the 1-MByte addressable range of the processorwhile in real-address mode. The processor is initialized to this starting address asfollows. The CS register has two parts: the visible segment selector part and thehidden base address part. In real-address mode, the base address is normallyformed by shifting the 16-bit segment selector value 4 bits to the left to produce a20-bit base address. However, during a hardware reset, the segment selector in theCS register is loaded with F000H and the base address is loaded with FFFF0000H. Thestarting address is thus formed by adding the base address to the value in the EIPregister (that is, FFFF0000 + FFF0H = FFFFFFF0H).The first time the CS register is loaded with a new value after a hardware reset, theprocessor will follow the normal rule for address translation in real-address mode(that is, [CS base address = CS segment selector * 16]).
To insure that the baseaddress in the CS register remains unchanged until the EPROM based softwareinitialization code is completed, the code must not contain a far jump or far call orallow an interrupt to occur (which would cause the CS selector value to be changed).9.2X87 FPU INITIALIZATIONSoftware-initialization code can determine the whether the processor contains anx87 FPU by using the CPUID instruction. The code must then initialize the x87 FPUand set flags in control register CR0 to reflect the state of the x87 FPU environment.A hardware reset places the x87 FPU in the state shown in Table 9-1. This state isdifferent from the state the x87 FPU is placed in following the execution of an FINITor FNINIT instruction (also shown in Table 9-1).
If the x87 FPU is to be used, the software-initialization code should execute an FINIT/FNINIT instruction following a hardware reset. These instructions, tag all data registers as empty, clear all the exceptionmasks, set the TOP-of-stack value to 0, and select the default rounding and precisioncontrols setting (round to nearest and 64-bit precision).If the processor is reset by asserting the INIT# pin, the x87 FPU state is not changed.9.2.1Configuring the x87 FPU EnvironmentInitialization code must load the appropriate values into the MP, EM, and NE flags ofcontrol register CR0.
These bits are cleared on hardware reset of the processor.Figure 9-2 shows the suggested settings for these flags, depending on the IA-32processor being initialized. Initialization code can test for the type of processorpresent before setting or clearing these flags.9-6 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONTable 9-2. Recommended Settings of EM and MP Flags on IA-32 ProcessorsEMMPNEIA-32 processor101011 or 0*Pentium 4, Intel Xeon, P6 family, Pentium, Intel486™ DX, andIntel 487 SX processors, and Intel386 DX and Intel386 SXprocessors when a companion math coprocessor is present.011 or 0*More recent Intel 64 or IA-32 processorsIntel486™ SX, Intel386™ DX, and Intel386™ SX processorsonly, without the presence of a math coprocessor.NOTE:* The setting of the NE flag depends on the operating system being used.The EM flag determines whether floating-point instructions are executed by the x87FPU (EM is cleared) or a device-not-available exception (#NM) is generated for allfloating-point instructions so that an exception handler can emulate the floatingpoint operation (EM = 1).
Ordinarily, the EM flag is cleared when an x87 FPU or mathcoprocessor is present and set if they are not present. If the EM flag is set and no x87FPU, math coprocessor, or floating-point emulator is present, the processor will hangwhen a floating-point instruction is executed.The MP flag determines whether WAIT/FWAIT instructions react to the setting of theTS flag. If the MP flag is clear, WAIT/FWAIT instructions ignore the setting of the TSflag; if the MP flag is set, they will generate a device-not-available exception (#NM)if the TS flag is set.
Generally, the MP flag should be set for processors with an integrated x87 FPU and clear for processors without an integrated x87 FPU and without amath coprocessor present. However, an operating system can choose to save thefloating-point context at every context switch, in which case there would be no needto set the MP bit.Table 2-1 shows the actions taken for floating-point and WAIT/FWAIT instructionsbased on the settings of the EM, MP, and TS flags.The NE flag determines whether unmasked floating-point exceptions are handled bygenerating a floating-point error exception internally (NE is set, native mode) orthrough an external interrupt (NE is cleared). In systems where an external interruptcontroller is used to invoke numeric exception handlers (such as MS-DOS-basedsystems), the NE bit should be cleared.9.2.2Setting the Processor for x87 FPU Software EmulationSetting the EM flag causes the processor to generate a device-not-available exception (#NM) and trap to a software exception handler whenever it encounters afloating-point instruction.
(Table 9-2 shows when it is appropriate to use this flag.)Setting this flag has two functions:Vol. 3 9-7PROCESSOR MANAGEMENT AND INITIALIZATION•It allows x87 FPU code to run on an IA-32 processor that has neither anintegrated x87 FPU nor is connected to an external math coprocessor, by using afloating-point emulator.•It allows floating-point code to be executed using a special or nonstandardfloating-point emulator, selected for a particular application, regardless ofwhether an x87 FPU or math coprocessor is present.To emulate floating-point instructions, the EM, MP, and NE flag in control register CR0should be set as shown in Table 9-3.Table 9-3. Software Emulation Settings of EM, MP, and NE FlagsCR0 BitValueEM1MP0NE1Regardless of the value of the EM bit, the Intel486 SX processor generates a devicenot-available exception (#NM) upon encountering any floating-point instruction.9.3CACHE ENABLINGIA-32 processors (beginning with the Intel486 processor) and Intel 64 processorscontain internal instruction and data caches.
These caches are enabled by clearingthe CD and NW flags in control register CR0. (They are set during a hardware reset.)Because all internal cache lines are invalid following reset initialization, it is notnecessary to invalidate the cache before enabling caching. Any external caches mayrequire initialization and invalidation using a system-specific initialization and invalidation code sequence.Depending on the hardware and operating system or executive requirements, additional configuration of the processor’s caching facilities will probably be required.Beginning with the Intel486 processor, page-level caching can be controlled with thePCD and PWT flags in page-directory and page-table entries.
Beginning with the P6family processors, the memory type range registers (MTRRs) control the cachingcharacteristics of the regions of physical memory. (For the Intel486 and Pentiumprocessors, external hardware can be used to control the caching characteristics ofregions of physical memory.) See Chapter 10, “Memory Cache Control,” for detailedinformation on configuration of the caching facilities in the Pentium 4, Intel Xeon, andP6 family processors and system memory.9-8 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATION9.4MODEL-SPECIFIC REGISTERS (MSRS)Most IA-32 processors (starting from Pentium processors) and Intel 64 processorscontain a model-specific registers (MSRs).
A given MSR may not be supported acrossall families and models for Intel 64 and IA-32 processors. Some MSRs are designatedas architectural to simplify software programming; a feature introduced by an architectural MSR is expected to be supported in future processors. Non-architecturalMSRs are not guaranteed to be supported or to have the same functions on futureprocessors.MSRs that provide control for a number of hardware and software-related features,include:•Performance-monitoring counters (see Section 18, “Debugging and PerformanceMonitoring”).••Debug extensions (see Section 18, “Debugging and Performance Monitoring”).••••MTRRs (see Section 10.11, “Memory Type Range Registers (MTRRs)”).Machine-check exception capability and its accompanying machine-check architecture (see Chapter 14, “Machine-Check Architecture”).Thermal and power management.Instruction-specific support (for example: SYSENTER, SYSEXIT, SWAPGS, etc.).Processor feature/mode support (for example: IA32_EFER,IA32_FEATURE_CONTROL).The MSRs can be read and written to using the RDMSR and WRMSR instructions,respectively.When performing software initialization of an IA-32 or Intel 64 processor, many ofthe MSRs will need to be initialized to set up things like performance-monitoringevents, run-time machine checks, and memory types for physical memory.Lists of available performance-monitoring events are given in Appendix A, “Performance Monitoring Events”, and lists of available MSRs are given in Appendix B,“Model-Specific Registers (MSRs)” The references earlier in this section show wherethe functions of the various groups of MSRs are described in this manual.9.5MEMORY TYPE RANGE REGISTERS (MTRRS)Memory type range registers (MTRRs) were introduced into the IA-32 architecturewith the Pentium Pro processor.
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