Volume 3A System Programming Guide_ Part 1 (794103), страница 91
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CorrectTrigger Modes must be guaranteed by software. Restrictions are indicated below:a. 000B (Fixed Mode) — Deliver the signal to all the agents listed in thedestination. The Trigger Mode for fixed delivery mode can be edge or level.b. 001B (Lowest Priority) — Deliver the signal to the agent that is executingat the lowest priority of all agents listed in the destination field. The triggermode can be edge or level.c.010B (System Management Interrupt or SMI) — The delivery mode isedge only. For systems that rely on SMI semantics, the vector field is ignoredbut must be programmed to all zeroes for future compatibility.d. 100B (NMI) — Deliver the signal to all the agents listed in the destinationfield.
The vector information is ignored. NMI is an edge triggered interruptregardless of the Trigger Mode Setting.e. 101B (INIT) — Deliver this signal to all the agents listed in the destinationfield. The vector information is ignored. INIT is an edge triggered interruptregardless of the Trigger Mode Setting.f.111B (ExtINT) — Deliver the signal to the INTR signal of all agents in thedestination field (as an interrupt that originated from an 8259A compatibleinterrupt controller). The vector is supplied by the INTA cycle issued by theactivation of the ExtINT. ExtINT is an edge triggered interrupt.3. Level — Edge triggered interrupt messages are always interpreted as assertmessages.
For edge triggered interrupts this field is not used. For level triggeredinterrupts, this bit reflects the state of the interrupt input.4. Trigger Mode — This field indicates the signal type that will trigger a message.a. 0 — Indicates edge sensitive.b. 1 — Indicates level sensitive.Vol. 3 8-49ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)8-50 Vol. 3CHAPTER 9PROCESSOR MANAGEMENT AND INITIALIZATIONThis chapter describes the facilities provided for managing processor wide functionsand for initializing the processor.
The subjects covered include: processor initialization, x87 FPU initialization, processor configuration, feature determination, modeswitching, the MSRs (in the Pentium, P6 family, Pentium 4, and Intel Xeon processors), and the MTRRs (in the P6 family, Pentium 4, and Intel Xeon processors).9.1INITIALIZATION OVERVIEWFollowing power-up or an assertion of the RESET# pin, each processor on the systembus performs a hardware initialization of the processor (known as a hardware reset)and an optional built-in self-test (BIST). A hardware reset sets each processor’sregisters to a known state and places the processor in real-address mode. It alsoinvalidates the internal caches, translation lookaside buffers (TLBs) and the branchtarget buffer (BTB). At this point, the action taken depends on the processor family:•Pentium 4 and Intel Xeon processors — All the processors on the system bus(including a single processor in a uniprocessor system) execute the multipleprocessor (MP) initialization protocol.
The processor that is selected through thisprotocol as the bootstrap processor (BSP) then immediately starts executingsoftware-initialization code in the current code segment beginning at the offset inthe EIP register. The application (non-BSP) processors (APs) go into a Wait ForStartup IPI (SIPI) state while the BSP is executing initialization code. See Section7.5, “Multiple-Processor (MP) Initialization,” for more details. Note that in auniprocessor system, the single Pentium 4 or Intel Xeon processor automaticallybecomes the BSP.•P6 family processors — The action taken is the same as for the Pentium 4 andIntel Xeon processors (as described in the previous paragraph).•Pentium processors — In either a single- or dual- processor system, a singlePentium processor is always pre-designated as the primary processor.
Followinga reset, the primary processor behaves as follows in both single- and dualprocessor systems. Using the dual-processor (DP) ready initialization protocol,the primary processor immediately starts executing software-initialization codein the current code segment beginning at the offset in the EIP register.
Thesecondary processor (if there is one) goes into a halt state.•Intel486 processor — The primary processor (or single processor in a uniprocessor system) immediately starts executing software-initialization code in thecurrent code segment beginning at the offset in the EIP register. (The Intel486does not automatically execute a DP or MP initialization protocol to determinewhich processor is the primary processor.)Vol.
3 9-1PROCESSOR MANAGEMENT AND INITIALIZATIONThe software-initialization code performs all system-specific initialization of the BSPor primary processor and the system logic.At this point, for MP (or DP) systems, the BSP (or primary) processor wakes up eachAP (or secondary) processor to enable those processors to execute self-configurationcode.When all processors are initialized, configured, and synchronized, the BSP or primaryprocessor begins executing an initial operating-system or executive task.The x87 FPU is also initialized to a known state during hardware reset.
x87 FPU software initialization code can then be executed to perform operations such as settingthe precision of the x87 FPU and the exception masks. No special initialization of thex87 FPU is required to switch operating modes.Asserting the INIT# pin on the processor invokes a similar response to a hardwarereset. The major difference is that during an INIT, the internal caches, MSRs, MTRRs,and x87 FPU state are left unchanged (although, the TLBs and BTB are invalidated aswith a hardware reset). An INIT provides a method for switching from protected toreal-address mode while maintaining the contents of the internal caches.9.1.1Processor State After ResetTable 9-1 shows the state of the flags and other registers following power-up for thePentium 4, Intel Xeon, P6 family, and Pentium processors.
The state of controlregister CR0 is 60000010H (see Figure 9-1). This places the processor is in realaddress mode with paging disabled.9.1.2Processor Built-In Self-Test (BIST)Hardware may request that the BIST be performed at power-up. The EAX register iscleared (0H) if the processor passes the BIST. A nonzero value in the EAX registerafter the BIST indicates that a processor fault was detected. If the BIST is notrequested, the contents of the EAX register after a hardware reset is 0H.The overhead for performing a BIST varies between processor families.
For example,the BIST takes approximately 30 million processor clock periods to execute on thePentium 4 processor. This clock count is model-specific; Intel reserves the right tochange the number of periods for any Intel 64 or IA-32 processor, without notification.Table 9-1. IA-32 Processor States Following Power-up, Reset, or INITRegisterPentium 4 and IntelXeon ProcessorP6 Family ProcessorPentium ProcessorEFLAGS100000002H00000002H00000002HEIP0000FFF0H0000FFF0H0000FFF0HCR09-2 Vol. 3260000010H260000010H60000010H2PROCESSOR MANAGEMENT AND INITIALIZATIONTable 9-1. IA-32 Processor States Following Power-up, Reset, or INIT (Contd.)RegisterPentium 4 and IntelXeon ProcessorP6 Family ProcessorPentium ProcessorCR2, CR3, CR400000000H00000000H00000000HCSSelector = F000HBase = FFFF0000HLimit = FFFFHAR = Present, R/W,AccessedSelector = F000HBase = FFFF0000HLimit = FFFFHAR = Present, R/W,AccessedSelector = F000HBase = FFFF0000HLimit = FFFFHAR = Present, R/W,AccessedSS, DS, ES, FS, GSSelector = 0000HBase = 00000000HLimit = FFFFHAR = Present, R/W,AccessedSelector = 0000HBase = 00000000HLimit = FFFFHAR = Present, R/W,AccessedSelector = 0000HBase = 00000000HLimit = FFFFHAR = Present, R/W,AccessedEDX00000FxxH000n06xxH3000005xxH40404EAX0EBX, ECX, ESI, EDI,EBP, ESP00000000H00000000H00000000HST0 through ST75Pwr up or Reset: +0.0FINIT/FNINIT: UnchangedPwr up or Reset: +0.0FINIT/FNINIT: UnchangedPwr up or Reset: +0.0FINIT/FNINIT: Unchangedx87 FPU ControlWord5Pwr up or Reset: 0040HFINIT/FNINIT: 037FHPwr up or Reset: 0040HFINIT/FNINIT: 037FHPwr up or Reset: 0040HFINIT/FNINIT: 037FHx87 FPU StatusWord5Pwr up or Reset: 0000HFINIT/FNINIT: 0000HPwr up or Reset: 0000HFINIT/FNINIT: 0000HPwr up or Reset: 0000HFINIT/FNINIT: 0000Hx87 FPU TagWord5Pwr up or Reset: 5555HFINIT/FNINIT: FFFFHPwr up or Reset: 5555HFINIT/FNINIT: FFFFHPwr up or Reset: 5555HFINIT/FNINIT: FFFFHx87 FPU DataOperand and CSSeg.
Selectors5Pwr up or Reset: 0000HFINIT/FNINIT: 0000HPwr up or Reset: 0000HFINIT/FNINIT: 0000HPwr up or Reset: 0000HFINIT/FNINIT: 0000Hx87 FPU DataOperand and Inst.Pointers5Pwr up or Reset:00000000HFINIT/FNINIT: 00000000HPwr up or Reset:00000000HFINIT/FNINIT: 00000000HPwr up or Reset:00000000HFINIT/FNINIT: 00000000HMM0 throughMM75Pwr up or Reset:0000000000000000HINIT or FINIT/FNINIT:UnchangedPentium II and Pentium IIIProcessors Only—Pwr up or Reset:0000000000000000HINIT or FINIT/FNINIT:UnchangedPentium with MMXTechnology Only—Pwr up or Reset:0000000000000000HINIT or FINIT/FNINIT:UnchangedXMM0 throughXMM7Pwr up or Reset:0000000000000000HINIT: UnchangedPentium III processor Only—Pwr up or Reset:0000000000000000HINIT: UnchangedNAMXCSRPwr up or Reset: 1F80HINIT: UnchangedPentium III processor onlyPwr up or Reset: 1F80HINIT: UnchangedNAGDTR, IDTRBase = 00000000HLimit = FFFFHAR = Present, R/WBase = 00000000HLimit = FFFFHAR = Present, R/WBase = 00000000HLimit = FFFFHAR = Present, R/WVol.
3 9-3PROCESSOR MANAGEMENT AND INITIALIZATIONTable 9-1. IA-32 Processor States Following Power-up, Reset, or INIT (Contd.)RegisterPentium 4 and IntelXeon ProcessorP6 Family ProcessorPentium ProcessorLDTR, TaskRegisterSelector = 0000HBase = 00000000HLimit = FFFFHAR = Present, R/WSelector = 0000HBase = 00000000HLimit = FFFFHAR = Present, R/WSelector = 0000HBase = 00000000HLimit = FFFFHAR = Present, R/WDR0, DR1, DR2,DR300000000H00000000H00000000HDR6FFFF0FF0HFFFF0FF0HFFFF0FF0HDR700000400H00000400H00000400HTime-StampCounterPower up or Reset: 0HINIT: UnchangedPower up or Reset: 0HINIT: UnchangedPower up or Reset: 0HINIT: UnchangedPerf. Counters andEvent SelectPower up or Reset: 0HINIT: UnchangedPower up or Reset: 0HINIT: UnchangedPower up or Reset: 0HINIT: UnchangedAll Other MSRsPwr up or Reset:UndefinedINIT: UnchangedPwr up or Reset:UndefinedINIT: UnchangedPwr up or Reset:UndefinedINIT: UnchangedData and CodeCache, TLBsInvalidInvalidInvalidFixed MTRRsPwr up or Reset: DisabledINIT: UnchangedPwr up or Reset: DisabledINIT: UnchangedNot ImplementedVariable MTRRsPwr up or Reset: DisabledINIT: UnchangedPwr up or Reset: DisabledINIT: UnchangedNot ImplementedMachine-CheckArchitecturePwr up or Reset:UndefinedINIT: UnchangedPwr up or Reset:UndefinedINIT: UnchangedNot ImplementedAPICPwr up or Reset: EnabledINIT: UnchangedPwr up or Reset: EnabledINIT: UnchangedPwr up or Reset: EnabledINIT: UnchangedNOTES:1.
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