Volume 3A System Programming Guide_ Part 1 (794103), страница 90
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Bits 4 through 7 of the thisfield are programmable by software, and bits 0 through 3 arehardwired to logical ones. Software writes to bits 0 through 3have no effect.APIC SoftwareAllows software to temporarily enable (1) or disable (0) the localEnable/DisableAPIC (see Section 8.4.3, “Enabling or Disabling the Local APIC”).Focus ProcessorDetermines if focus processor checking is enabled (0) ordisabled (1)Checkingwhen using the lowest-priority delivery mode.
In Pentium 4 andIntel Xeon processors, this bit is reserved and should be clearedto 0.NOTEDo not program an LVT or IOAPIC RTE with a spurious vector even ifyou set the mask bit. A spurious vector ISR does not do an EOI. If forsome reason an interrupt is generated by an LVT or RTE entry, the bitin the in-service register will be left set for the spurious vector. Thiswill mask all interrupts at the same or lower priority8-44 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)3110 9 8 70ReservedFocus Processor Checking10: Enabled1: DisabledAPIC Software Enable/Disable0: APIC Disabled1: APIC EnabledSpurious Vector2Address: FEE0 00F0HValue after reset: 0000 00FFH1.
Not supported in Pentium 4 and Intel Xeon processors.2. For the P6 family and Pentium processors, bits 0 through 3of the spurious vector are hardwired to 1.Figure 8-23. Spurious-Interrupt Vector Register (SVR)8.10APIC BUS MESSAGE PASSING MECHANISM ANDPROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)The Pentium 4 and Intel Xeon processors pass messages among the local and I/OAPICs on the system bus, using the system bus message passing mechanism andprotocol.The P6 family and Pentium processors, pass messages among the local and I/OAPICs on the serial APIC bus, as follows.
Because only one message can be sent at atime on the APIC bus, the I/O APIC and local APICs employ a “rotating priority” arbitration protocol to gain permission to send a message on the APIC bus. One or moreAPICs may start sending their messages simultaneously. At the beginning of everymessage, each APIC presents the type of the message it is sending and its currentarbitration priority on the APIC bus. This information is used for arbitration.
Aftereach arbitration cycle (within an arbitration round), only the potential winners keepdriving the bus. By the time all arbitration cycles are completed, there will be onlyone APIC left driving the bus. Once a winner is selected, it is granted exclusive use ofthe bus, and will continue driving the bus to send its actual message.After each successfully transmitted message, all APICs increase their arbitrationpriority by 1.
The previous winner (that is, the one that has just successfully transmitted its message) assumes a priority of 0 (lowest). An agent whose arbitrationpriority was 15 (highest) during arbitration, but did not send a message, adopts theprevious winner’s arbitration priority, increments by 1.Note that the arbitration protocol described above is slightly different if one of theAPICs issues a special End-Of-Interrupt (EOI). This high-priority message is grantedVol.
3 8-45ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)the bus regardless of its sender’s arbitration priority, unless more than one APICissues an EOI message simultaneously. In the latter case, the APICs sending the EOImessages arbitrate using their arbitration priorities.If the APICs are set up to use “lowest priority” arbitration (see Section 8.6.2.4,“Lowest Priority Delivery Mode”) and multiple APICs are currently executing at thelowest priority (the value in the APR register), the arbitration priorities (uniquevalues in the Arb ID register) are used to break ties. All 8 bits of the APR are used forthe lowest priority arbitration.8.10.1Bus Message FormatsSee Appendix F, “APIC Bus Message Formats,” for a description of bus messageformats used to transmit messages on the serial APIC bus.8.11MESSAGE SIGNALLED INTERRUPTSThe PCI Local Bus Specification, Rev 2.2 (www.pcisig.com) introduces the concept ofmessage signalled interrupts.
Intel processors and chipsets with this capabilitycurrently include the Pentium 4 and Intel Xeon processors. As the specification indicates:“Message signalled interrupts (MSI) is an optional feature thatenables PCI devices to request service by writing a system-specifiedmessage to a system-specified address (PCI DWORD memory writetransaction). The transaction address specifies the messagedestination while the transaction data specifies the message.
Systemsoftware is expected to initialize the message destination andmessage during device configuration, allocating one or more nonshared messages to each MSI capable function.”The capabilities mechanism provided by the PCI Local Bus Specification is used toidentify and configure MSI capable PCI devices. Among other fields, this structurecontains a Message Data Register and a Message Address Register. To requestservice, the PCI device function writes the contents of the Message Data Register tothe address contained in the Message Address Register (and the Message UpperAddress register for 64-bit message addresses).Section 8.11.1 and Section 8.11.2 provide layout details for the Message AddressRegister and the Message Data Register. The operation issued by the device is a PCIwrite command to the Message Address Register with the Message Data Registercontents.
The operation follows semantic rules as defined for PCI write operationsand is a DWORD operation.8-46 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)8.11.1Message Address Register FormatThe format of the Message Address Register (lower 32-bits) is shown in Figure 8-24.3120 190FEEH12 11Destination ID4Reserved32RHDM10XXFigure 8-24. Layout of the MSI Message Address RegisterFields in the Message Address Register are as follows:1. Bits 31-20 — These bits contain a fixed value for interrupt messages (0FEEH).This value locates interrupts at the 1-MByte area with a base address of 4G –18M. All accesses to this region are directed as interrupt messages.
Care must tobe taken to ensure that no other device claims the region as I/O space.2. Destination ID — This field contains an 8-bit destination ID. It identifies themessage’s target processor(s). The destination ID corresponds to bits 63:56 ofthe I/O APIC Redirection Table Entry if the IOAPIC is used to dispatch theinterrupt to the processor(s).3. Redirection hint indication (RH) — This bit indicates whether the messageshould be directed to the processor with the lowest interrupt priority amongprocessors that can receive the interrupt.•When RH is 0, the interrupt is directed to the processor listed in theDestination ID field.•When RH is 1 and the physical destination mode is used, the DestinationID field must not be set to 0xFF; it must point to a processor that ispresent and enabled to receive the interrupt.•When RH is 1 and the logical destination mode is active in a system usinga flat addressing model, the Destination ID field must be set so that bitsset to 1 identify processors that are present and enabled to receive theinterrupt.•If RH is set to 1 and the logical destination mode is active in a systemusing cluster addressing model, then Destination ID field must not be setto 0xFF; the processors identified with this field must be present andenabled to receive the interrupt.4.
Destination mode (DM) — This bit indicates whether the Destination ID fieldshould be interpreted as logical or physical APIC ID for delivery of the lowestpriority interrupt. If RH is 1 and DM is 0, the Destination ID field is in physicaldestination mode and only the processor in the system that has the matchingVol. 3 8-47ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)APIC ID is considered for delivery of that interrupt (this means no re-direction).If RH is 1 and DM is 1, the Destination ID Field is interpreted as in logicaldestination mode and the redirection is limited to only those processors that arepart of the logical group of processors based on the processor’s logical APIC IDand the Destination ID field in the message.
The logical group of processorsconsists of those identified by matching the 8-bit Destination ID with the logicaldestination identified by the Destination Format Register and the LogicalDestination Register in each local APIC. The details are similar to those describedin Section 8.6.2, “Determining IPI Destination.” If RH is 0, then the DM bit isignored and the message is sent ahead independent of whether the physical orlogical destination mode is used.8.11.2Message Data Register FormatThe layout of the Message Data Register is shown in Figure 8-25.6332Reserved311615ReservedTrigger Mode0 - Edge1 - LevelLevel for Trigger Mode = 0X - Don’t careLevel for Trigger Mode = 10 - Deassert1 - Assert1413Reserved11 10870VectorDelivery Mode000 - Fixed001 - Lowest Priority010 - SMI011 - Reserved001 - NMI101 - INIT110 - Reserved111 - ExtINTFigure 8-25.
Layout of the MSI Message Data RegisterReserved fields are not assumed to be any value. Software must preserve theircontents on writes. Other fields in the Message Data Register are described below.8-48 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)1. Vector — This 8-bit field contains the interrupt vector associated with themessage. Values range from 010H to 0FEH. Software must guarantee that thefield is not programmed with vector 00H to 0FH.2. Delivery Mode — This 3-bit field specifies how the interrupt receipt is handled.Delivery Modes operate only in conjunction with specified Trigger Modes.
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