Volume 3A System Programming Guide_ Part 1 (794103), страница 94
Текст из файла (страница 94)
As with descriptors for LDTs, TSS descriptorsreside in the GDT.After the processor has switched to protected mode, the LTR instruction can be usedto load a segment selector for a TSS descriptor into the task register. This instructionmarks the TSS descriptor as busy, but does not perform a task switch. The processorcan, however, use the TSS to locate pointers to privilege-level 0, 1, and 2 stacks. Thesegment selector for the TSS must be loaded before software performs its first taskswitch in protected mode, because a task switch copies the current task state intothe TSS.After the LTR instruction has been executed, further operations on the task registerare performed by task switching.
As with other segments and LDTs, TSSs and TSSdescriptors can be either pre-allocated or allocated as needed.9.8.5Initializing IA-32e ModeOn Intel 64 processors, the IA32_EFER MSR is cleared on system reset. The operating system must be in protected mode with paging enabled before attempting toinitialize IA-32e mode. IA-32e mode operation also requires physical-address extensions with four levels of enhanced paging structures (see Section 3.10, “PAE-EnabledPaging in IA-32e Mode”).Operating systems should follow this sequence to initialize IA-32e mode:1. Starting from protected mode, disable paging by setting CR0.PG = 0.
Use theMOV CR0 instruction to disable paging (the instruction must be located in anidentity-mapped page).2. Enable physical-address extensions (PAE) by setting CR4.PAE = 1. Failure toenable PAE will result in a #GP fault when an attempt is made to initialize IA-32emode.3. Load CR3 with the physical base address of the Level 4 page map table (PML4).4. Enable IA-32e mode by setting IA32_EFER.LME = 1.5.
Enable paging by setting CR0.PG = 1. This causes the processor to set theIA32_EFER.LMA bit to 1. The MOV CR0 instruction that enables paging and the9-14 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONfollowing instructions must be located in an identity-mapped page (until suchtime that a branch to non-identity mapped pages can be effected).64-bit mode paging tables must be located in the first 4 GBytes of physical-addressspace prior to activating IA-32e mode. This is necessary because the MOV CR3instruction used to initialize the page-directory base must be executed in legacymode prior to activating IA-32e mode (setting CR0.PG = 1 to enable paging).Because MOV CR3 is executed in protected mode, only the lower 32 bits of theregister are written, limiting the table location to the low 4 GBytes of memory. Software can relocate the page tables anywhere in physical memory after IA-32e modeis activated.The processor performs 64-bit mode consistency checks whenever softwareattempts to modify any of the enable bits directly involved in activating IA-32e mode(IA32_EFER.LME, CR0.PG, and CR4.PAE).
It will generate a general protection fault(#GP) if consistency checks fail. 64-bit mode consistency checks ensure that theprocessor does not enter an undefined mode or state with unpredictable behavior.64-bit mode consistency checks fail in the following circumstances:••An attempt is made to enable or disable IA-32e mode while paging is enabled.•IA-32e mode is active and an attempt is made to disable physical-addressextensions (PAE).••If the current CS has the L-bit set on an attempt to activate IA-32e mode.IA-32e mode is enabled and an attempt is made to enable paging prior toenabling physical-address extensions (PAE).The TR must contain a 16-bit TSS.9.8.5.1IA-32e Mode System Data StructuresAfter activating IA-32e mode, the system-descriptor-table registers (GDTR, LDTR,IDTR, TR) continue to reference legacy protected-mode descriptor tables.
Tablesreferenced by the descriptors all reside in the lower 4 GBytes of linear-address space.After activating IA-32e mode, 64-bit operating-systems should use the LGDT, LLDT,LIDT, and LTR instructions to load the system-descriptor-table registers with references to 64-bit descriptor tables.9.8.5.2IA-32e Mode Interrupts and ExceptionsSoftware must not allow exceptions or interrupts to occur between the time IA-32emode is activated and the update of the interrupt-descriptor-table register (IDTR)that establishes references to a 64-bit interrupt-descriptor table (IDT). This isbecause the IDT remains in legacy form immediately after IA-32e mode is activated.If an interrupt or exception occurs prior to updating the IDTR, a legacy 32-bit interrupt gate will be referenced and interpreted as a 64-bit interrupt gate with unpredictable results.
External interrupts can be disabled by using the CLI instruction.Non-maskable interrupts (NMI) must be disabled using external hardware.Vol. 3 9-15PROCESSOR MANAGEMENT AND INITIALIZATION9.8.5.364-bit Mode and Compatibility Mode OperationIA-32e mode uses two code segment-descriptor bits (CS.L and CS.D, see Figure 3-8)to control the operating modes after IA-32e mode is initialized. If CS.L = 1 and CS.D =0, the processor is running in 64-bit mode. With this encoding, the default operandsize is 32 bits and default address size is 64 bits. Using instruction prefixes, operandsize can be changed to 64 bits or 16 bits; address size can be changed to 32 bits.When IA-32e mode is active and CS.L = 0, the processor operates in compatibilitymode. In this mode, CS.D controls default operand and address sizes exactly as itdoes in the IA-32 architecture.
Setting CS.D = 1 specifies default operand andaddress size as 32 bits. Clearing CS.D to 0 specifies default operand and address sizeas 16 bits (the CS.L = 1, CS.D = 1 bit combination is reserved).Compatibility mode execution is selected on a code-segment basis. This mode allowslegacy applications to coexist with 64-bit applications running in 64-bit mode. Anoperating system running in IA-32e mode can execute existing 16-bit and 32-bitapplications by clearing their code-segment descriptor’s CS.L bit to 0.In compatibility mode, the following system-level mechanisms continue to operateusing the IA-32e-mode architectural semantics:•Linear-to-physical address translation uses the 64-bit mode extended pagetranslation mechanism.••Interrupts and exceptions are handled using the 64-bit mode mechanisms.System calls (calls through call gates and SYSENTER/SYSEXIT) are handled usingthe IA-32e mode mechanisms.9.8.5.4Switching Out of IA-32e Mode OperationTo return from IA-32e mode to paged-protected mode operation.
Operating systemsmust use the following sequence:1. Switch to compatibility mode.2. Deactivate IA-32e mode by clearing CR0.PG = 0. This causes the processor to setIA32_EFER.LMA = 0. The MOV CR0 instruction used to disable paging andsubsequent instructions must be located in an identity-mapped page.3. Load CR3 with the physical base address of the legacy page-table-directory baseaddress.4.
Disable IA-32e mode by setting IA32_EFER.LME = 0.5. Enable legacy paged-protected mode by setting CR0.PG = 16. A branch instruction must follow the MOV CR0 that enables paging. Both the MOVCR0 and the branch instruction must be located in an identity-mapped page.Registers only available in 64-bit mode (R8-R15 and XMM8-XMM15) are preservedacross transitions from 64-bit mode into compatibility mode then back into 64-bitmode.
However, values of R8-R15 and XMM8-XMM15 are undefined after transitions9-16 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONfrom 64-bit mode through compatibility mode to legacy or real mode and then backthrough compatibility mode to 64-bit mode.9.9MODE SWITCHINGTo use the processor in protected mode after hardware or software reset, a modeswitch must be performed from real-address mode. Once in protected mode, software generally does not need to return to real-address mode.
To run software writtento run in real-address mode (8086 mode), it is generally more convenient to run thesoftware in virtual-8086 mode, than to switch back to real-address mode.9.9.1Switching to Protected ModeBefore switching to protected mode from real mode, a minimum set of system datastructures and code modules must be loaded into memory, as described in Section9.8, “Software Initialization for Protected-Mode Operation.” Once these tables arecreated, software initialization code can switch into protected mode.Protected mode is entered by executing a MOV CR0 instruction that sets the PE flagin the CR0 register.
(In the same instruction, the PG flag in register CR0 can be set toenable paging.) Execution in protected mode begins with a CPL of 0.Intel 64 and IA-32 processors have slightly different requirements for switching toprotected mode. To insure upwards and downwards code compatibility with Intel 64and IA-32 processors, we recommend that you follow these steps:1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMIinterrupts can be disabled with external circuitry.
(Software must guarantee thatno exceptions or interrupts are generated during the mode switching operation.)2. Execute the LGDT instruction to load the GDTR register with the base address ofthe GDT.3. Execute a MOV CR0 instruction that sets the PE flag (and optionally the PG flag)in control register CR0.4. Immediately following the MOV CR0 instruction, execute a far JMP or far CALLinstruction. (This operation is typically a far jump or call to the next instruction inthe instruction stream.)5.
The JMP or CALL instruction immediately after the MOV CR0 instruction changesthe flow of execution and serializes the processor.6. If paging is enabled, the code for the MOV CR0 instruction and the JMP or CALLinstruction must come from a page that is identity mapped (that is, the linearaddress before the jump is the same as the physical address after paging andprotected mode is enabled). The target instruction for the JMP or CALL instructiondoes not need to be identity mapped.Vol. 3 9-17PROCESSOR MANAGEMENT AND INITIALIZATION7. If a local descriptor table is going to be used, execute the LLDT instruction to loadthe segment selector for the LDT in the LDTR register.8. Execute the LTR instruction to load the task register with a segment selector tothe initial protected-mode task or to a writable area of memory that can be usedto store TSS information on a task switch.9.
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