Volume 3A System Programming Guide_ Part 1 (794103), страница 95
Текст из файла (страница 95)
After entering protected mode, the segment registers continue to hold thecontents they had in real-address mode. The JMP or CALL instruction in step 4resets the CS register. Perform one of the following operations to update thecontents of the remaining segment registers.— Reload segment registers DS, SS, ES, FS, and GS. If the ES, FS, and/or GSregisters are not going to be used, load them with a null selector.— Perform a JMP or CALL instruction to a new task, which automatically resetsthe values of the segment registers and branches to a new code segment.10.
Execute the LIDT instruction to load the IDTR register with the address and limitof the protected-mode IDT.11. Execute the STI instruction to enable maskable hardware interrupts and performthe necessary hardware operation to enable NMI interrupts.Random failures can occur if other instructions exist between steps 3 and 4 above.Failures will be readily seen in some situations, such as when instructions that reference memory are inserted between steps 3 and 4 while in system managementmode.9.9.2Switching Back to Real-Address ModeThe processor switches from protected mode back to real-address mode if softwareclears the PE bit in the CR0 register with a MOV CR0 instruction. A procedure that reenters real-address mode should perform the following steps:1. Disable interrupts.
A CLI instruction disables maskable hardware interrupts. NMIinterrupts can be disabled with external circuitry.2. If paging is enabled, perform the following operations:— Transfer program control to linear addresses that are identity mapped tophysical addresses (that is, linear addresses equal physical addresses).— Insure that the GDT and IDT are in identity mapped pages.— Clear the PG bit in the CR0 register.— Move 0H into the CR3 register to flush the TLB.3. Transfer program control to a readable segment that has a limit of 64 KBytes(FFFFH). This operation loads the CS register with the segment limit required inreal-address mode.9-18 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATION4. Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptorcontaining the following values, which are appropriate for real-address mode:— Limit = 64 KBytes (0FFFFH)— Byte granular (G = 0)— Expand up (E = 0)— Writable (W = 1)— Present (P = 1)— Base = any value5. The segment registers must be loaded with non-null segment selectors or thesegment registers will be unusable in real-address mode.
Note that if thesegment registers are not reloaded, execution continues using the descriptorattributes loaded during protected mode.6. Execute an LIDT instruction to point to a real-address mode interrupt table that iswithin the 1-MByte real-address mode address range.7. Clear the PE flag in the CR0 register to switch to real-address mode.8.
Execute a far JMP instruction to jump to a real-address mode program. Thisoperation flushes the instruction queue and loads the appropriate base andaccess rights values in the CS register.9. Load the SS, DS, ES, FS, and GS registers as needed by the real-address modecode. If any of the registers are not going to be used in real-address mode, write0s to them.10.
Execute the STI instruction to enable maskable hardware interrupts and performthe necessary hardware operation to enable NMI interrupts.NOTEAll the code that is executed in steps 1 through 9 must be in a singlepage and the linear addresses in that page must be identity mappedto physical addresses.9.10INITIALIZATION AND MODE SWITCHING EXAMPLEThis section provides an initialization and mode switching example that can be incorporated into an application. This code was originally written to initialize the Intel386processor, but it will execute successfully on the Pentium 4, Intel Xeon, P6 family,Pentium, and Intel486 processors.
The code in this example is intended to reside inEPROM and to run following a hardware reset of the processor. The function of thecode is to do the following:••Establish a basic real-address mode operating environment.Load the necessary protected-mode system data structures into RAM.Vol. 3 9-19PROCESSOR MANAGEMENT AND INITIALIZATION•Load the system registers with the necessary pointers to the data structures andthe appropriate flag settings for protected-mode operation.•Switch the processor to protected mode.Figure 9-3 shows the physical memory layout for the processor following a hardwarereset and the starting point of this example. The EPROM that contains the initialization code resides at the upper end of the processor’s physical memory address range,starting at address FFFFFFFFH and going down from there.
The address of the firstinstruction to be executed is at FFFFFFF0H, the default starting address for theprocessor following a hardware reset.The main steps carried out in this example are summarized in Table 9-4. The sourcelisting for the example (with the filename STARTUP.ASM) is given in Example 9-1.The line numbers given in Table 9-4 refer to the source listing.The following are some additional notes concerning this example:•When the processor is switched into protected mode, the original code segmentbase-address value of FFFF0000H (located in the hidden part of the CS register)is retained and execution continues from the current offset in the EIP register.The processor will thus continue to execute code in the EPROM until a far jump orcall is made to a new code segment, at which time, the base address in the CSregister will be changed.•Maskable hardware interrupts are disabled after a hardware reset and shouldremain disabled until the necessary interrupt handlers have been installed.
TheNMI interrupt is not disabled following a reset. The NMI# pin must thus beinhibited from being asserted until an NMI handler has been loaded and madeavailable to the processor.•The use of a temporary GDT allows simple transfer of tables from the EPROM toanywhere in the RAM area. A GDT entry is constructed with its base pointing toaddress 0 and a limit of 4 GBytes. When the DS and ES registers are loaded withthis descriptor, the temporary GDT is no longer needed and can be replaced bythe application GDT.•This code loads one TSS and no LDTs. If more TSSs exist in the application, theymust be loaded into RAM. If there are LDTs they may be loaded as well.9-20 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATIONAfter Reset[CS.BASE+EIP]FFFF FFFFHFFFF FFF0H64K EPROMEIP = 0000 FFF0HCS.BASE = FFFF 0000HDS.BASE = 0HES.BASE = 0HSS.BASE = 0HESP = 0H[SP, DS, SS, ES]FFFF 0000H0Figure 9-3.
Processor State After ResetTable 9-4. Main Initialization Steps in STARTUP.ASM Source ListingSTARTUP.ASM LineNumbersDescriptionFromTo157157Jump (short) to the entry code in the EPROM162169Construct a temporary GDT in RAM with one entry:0 - null1 - R/W data segment, base = 0, limit = 4 GBytes171172Load the GDTR to point to the temporary GDT174177Load CR0 with PE flag set to switch to protected mode179181Jump near to clear real mode instruction queue184186Load DS, ES registers with GDT[1] descriptor, so both point to theentire physical memory spaceVol.
3 9-21PROCESSOR MANAGEMENT AND INITIALIZATIONTable 9-4. Main Initialization Steps in STARTUP.ASM Source Listing (Contd.)STARTUP.ASM LineNumbersDescriptionFromTo188195Perform specific board initialization that is imposed by the newprotected mode196218Copy the application's GDT from ROM into RAM220238Copy the application's IDT from ROM into RAM241243Load application's GDTR244245Load application's IDTR247261Copy the application's TSS from ROM into RAM263267Update TSS descriptor and other aliases in GDT (GDT alias or IDTalias)277277Load the task register (without task switch) using LTR instruction282286Load SS, ESP with the value found in the application's TSS287287Push EFLAGS value found in the application's TSS288288Push CS value found in the application's TSS289289Push EIP value found in the application's TSS290293Load DS, ES with the value found in the application's TSS296296Perform IRET; pop the above values and enter the application code9.10.1Assembler UsageIn this example, the Intel assembler ASM386 and build tools BLD386 are used toassemble and build the initialization code module.
The following assumptions areused when using the Intel ASM386 and BLD386 tools.•The ASM386 will generate the right operand size opcodes according to the codesegment attribute. The attribute is assigned either by the ASM386 invocationcontrols or in the code-segment definition.•If a code segment that is going to run in real-address mode is defined, it must beset to a USE 16 attribute.
If a 32-bit operand is used in an instruction in this codesegment (for example, MOV EAX, EBX), the assembler automatically generatesan operand prefix for the instruction that forces the processor to execute a 32-bitoperation, even though its default code-segment attribute is 16-bit.•Intel's ASM386 assembler allows specific use of the 16- or 32-bit instructions, forexample, LGDTW, LGDTD, IRETD.
If the generic instruction LGDT is used, thedefault- segment attribute will be used to generate the right opcode.9-22 Vol. 3PROCESSOR MANAGEMENT AND INITIALIZATION9.10.2STARTUP.ASM ListingExample 9-1 provides high-level sample code designed to move the processor intoprotected mode. This listing does not include any opcode and offset information.Example 9-1.
STARTUP.ASMMS-DOS* 5.0(045-N) 386(TM) MACRO ASSEMBLER STARTUPPAGE 109:44:51 08/19/92MS-DOS 5.0(045-N) 386(TM) MACRO ASSEMBLER V4.0, ASSEMBLY OF MODULESTARTUPOBJECT MODULE PLACED IN startup.objASSEMBLER INVOKED BY: f:\386tools\ASM386.EXE startup.a58 pw (132 )LINE123456789101112131415161718192021222324252627SOURCENAMESTARTUP;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;ASSUMPTIONS:;;1. The bottom 64K of memory is ram, and can be used for;scratch space by this module.;;2.
The system has sufficient free usable ram to copy the;initial GDT, IDT, and TSS;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; configuration data - must match with build definitionCS_BASEEQU0FFFF0000H; CS_BASE is the linear address of the segment STARTUP_CODE; - this is specified in the build language fileRAM_START;;;;EQU400HRAM_START is the start of free, usable ram in the linearmemory space.The GDT, IDT, and initial TSS will becopied above this space, and a small data segment will bediscarded at this linear address.The 32-bit word atVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
