Volume 3A System Programming Guide_ Part 1 (794103), страница 99
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The BIOS is responsible for ensuringthat this requirement is met and that the loader is located in a module executed byall processors in the system. If a system design permits multiple steppings ofPentium 4, Intel Xeon, and P6 family processors to exist concurrently; then the BIOSmust verify individual processors against the update header information to ensureappropriate loading. Given these considerations, it is most practical to load theupdate during MP initialization.9.11.6.3Update in a System Supporting Intel Hyper-Threading TechnologyIntel Hyper-Threading Technology has implications on the loading of the microcodeupdate. The update must be loaded for each core in a physical processor. Thus, for aprocessor supporting Hyper-Threading Technology, only one logical processor percore is required to load the microcode update.
Each individual logical processor canindependently load the update. However, MP initialization must provide some mechanism (e.g. a software semaphore) to force serialization of microcode update loadsand to prevent simultaneous load attempts to the same core.9.11.6.4Update in a System Supporting Dual-Core TechnologyDual-core technology has implications on the loading of the microcode update. Themicrocode update facility is not shared between processor cores in the same physicalpackage. The update must be loaded for each core in a physical processor.9-46 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATIONIf processor core supports Hyper-Threading Technology, the guideline described inSection 9.11.6.3 also applies.9.11.6.5Update Loader EnhancementsThe update loader presented in Section 9.11.6, “Microcode Update Loader,” is aminimal implementation that can be enhanced to provide additional functionality.Potential enhancements are described below:•BIOS can incorporate multiple updates to support multiple steppings of thePentium 4, Intel Xeon, and P6 family processors. This feature provides foroperating in a mixed stepping environment on an MP system and enables a userto upgrade to a later version of the processor. In this case, modify the loader tocheck the CPUID and platform ID bits of the processor that it is running onagainst the available headers before loading a particular update.
The number ofupdates is only limited by available BIOS space.•A loader can load the update and test the processor to determine if the updatewas loaded correctly. See Section 9.11.7, “Update Signature and Verification.”•A loader can verify the integrity of the update data by performing a checksum onthe double words of the update summing to zero. See Section 9.11.5, “MicrocodeUpdate Checksum.”•A loader can provide power-on messages indicating successful loading of anupdate.9.11.7Update Signature and VerificationThe Pentium 4, Intel Xeon, and P6 family processors provide capabilities to verify theauthenticity of a particular update and to identify the current update revision. Thissection describes the model-specific extensions of processors that support thisfeature.
The update verification method below assumes that the BIOS will only verifyan update that is more recent than the revision currently loaded in the processor.CPUID returns a value in a model specific register in addition to its usual registerreturn values. The semantics of CPUID cause it to deposit an update ID value in the64-bit model-specific register at address 08BH (IA32_BIOS_SIGN_ID). If no updateis present in the processor, the value in the MSR remains unmodified. The BIOS mustpre-load a zero into the MSR before executing CPUID. If a read of the MSR at 8BH stillreturns zero after executing CPUID, this indicates that no update is present.The update ID value returned in the EDX register after RDMSR executes indicates therevision of the update loaded in the processor.
This value, in combination with theCPUID value returned in the EAX register, uniquely identifies a particular update. Thesignature ID can be directly compared with the update revision field in a microcodeupdate header for verification of a correct load. No consecutive updates released fora given stepping of a processor may share the same signature. The processor signature returned by CPUID differentiates updates for different steppings.Vol. 3 9-47PROCESSOR MANAGEMENT AND INITIALIZATION9.11.7.1Determining the SignatureAn update that is successfully loaded into the processor provides a signature thatmatches the update revision of the currently functioning revision. This signature isavailable any time after the actual update has been loaded.
Requesting the signaturedoes not have a negative impact upon a loaded update.The procedure for determining this signature shown in Example 9-9.Example 9-9. Assembly Code to Retrieve the Update RevisionMOVXORXORWRMSRMOVcpuidMOVrdmsrECX, 08BHEAX, EAXEDX, EDX;IA32_BIOS_SIGN_ID;clear EAX;clear EDX;Load 0 to MSR at 8BHEAX, 1ECX, 08BH;IA32_BIOS_SIGN_ID;Read Model Specific RegisterIf there is an update active in the processor, its revision is returned in the EDXregister after the RDMSR instruction executes.IA32_BIOS_SIGN_IDMSR Address:Default Value:Access:Microcode Update Signature Register08BH Accessed as a QwordXXXX XXXX XXXX XXXXhRead/WriteThe IA32_BIOS_SIGN_ID register is used to report the microcode update signaturewhen CPUID executes.
The signature is returned in the upper DWORD (Table 9-11).Table 9-11. Microcode Update SignatureBitDescription63:32Microcode update signature. This field contains the signature of the currently loadedmicrocode update when read following the execution of the CPUID instruction, function1. It is required that this register field be pre-loaded with zero prior to executing theCPUID, function 1. If the field remains equal to zero, then there is no microcode updateloaded. Another non-zero value will be the signature.31:0Reserved.9.11.7.2Authenticating the UpdateAn update may be authenticated by the BIOS using the signature primitive,described above, and the algorithm in Example 9-10.9-48 Vol.
3PROCESSOR MANAGEMENT AND INITIALIZATIONExample 9-10. Pseudo Code to Authenticate the UpdateZ ← Obtain Update Revision from the Update Header to be authenticated;X ← Obtain Current Update Signature from MSR 8BH;If (Z > X){Load Update that is to be authenticated;Y ← Obtain New Signature from MSR 8BH;If (Z == Y)SuccessElseFail}ElseFailExample 9-10 requires that the BIOS only authenticate updates that contain anumerically larger revision than the currently loaded revision, where Current Signature (X) < New Update Revision (Z). A processor with no loaded update is consideredto have a revision equal to zero.This authentication procedure relies upon the decoding provided by the processor toverify an update from a potentially hostile source.
As an example, this mechanism inconjunction with other safeguards provides security for dynamically incorporatingfield updates into the BIOS.9.11.8Pentium 4, Intel Xeon, and P6 Family ProcessorMicrocode Update SpecificationsThis section describes the interface that an application can use to dynamically integrate processor-specific updates into the system BIOS. In this discussion, the application is referred to as the calling program or caller.The real mode INT15 call specification described here is an Intel extension to an OEMBIOS. This extension allows an application to read and modify the contents of themicrocode update data in NVRAM.
The update loader, which is part of the systemBIOS, cannot be updated by the interface. All of the functions defined in the specification must be implemented for a system to be considered compliant with the specification. The INT15 functions are accessible only from real mode.9.11.8.1Responsibilities of the BIOSIf a BIOS passes the presence test (INT 15H, AX = 0D042H, BL = 0H), it must implement all of the sub-functions defined in the INT 15H, AX = 0D042H specification.Vol. 3 9-49PROCESSOR MANAGEMENT AND INITIALIZATIONThere are no optional functions. BIOS must load the appropriate update for eachprocessor during system initialization.A Header Version of an update block containing the value 0FFFFFFFFH indicates thatthe update block is unused and available for storing a new update.The BIOS is responsible for providing a region of non-volatile storage (NVRAM) foreach potential processor stepping within a system.
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