Volume 3A System Programming Guide_ Part 1 (794103), страница 82
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Local APICs and I/O APIC When P6 Family Processors Are Used inMultiple-Processor Systems8-4 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)The IPI mechanism is typically used in MP systems to send fixed interrupts (interrupts for a specific vector number) and special-purpose interrupts to processors onthe system bus. For example, a local APIC can use an IPI to forward a fixed interruptto another processor for servicing.
Special-purpose IPIs (including NMI, INIT, SMIand SIPI IPIs) allow one or more processors on the system bus to perform systemwide boot-up and control functions.The following sections focus on the local APIC and its implementation in thePentium 4, Intel Xeon, and P6 family processors. In these sections, the terms “localAPIC” and “I/O APIC” refer to local and I/O APICs used with the P6 family processorsand to local and I/O xAPICs used with the Pentium 4 and Intel Xeon processors (seeSection 8.3, “the Intel® 82489DX External APIC, The APIC, and the xAPIC”).8.2SYSTEM BUS VS.
APIC BUSFor the P6 family and Pentium processors, the I/O APIC and local APICs communicatethrough the 3-wire inter-APIC bus (see Figure 8-3). Local APICs also use the APICbus to send and receive IPIs. The APIC bus and its messages are invisible to softwareand are not classed as architectural.Beginning with the Pentium 4 and Intel Xeon processors, the I/O APIC and localAPICs (using the xAPIC architecture) communicate through the system bus (seeFigure 8-2). The I/O APIC sends interrupt requests to the processors on the systembus through bridge hardware that is part of the Intel chip set.
The bridge hardwaregenerates the interrupt messages that go to the local APICs. IPIs between localAPICs are transmitted directly on the system bus.8.3THE INTEL® 82489DX EXTERNAL APIC,THE APIC, AND THE XAPICThe local APIC in the P6 family and Pentium processors is an architectural subset ofthe Intel® 82489DX external APIC.
See Section 17.26.1, “Software Visible Differences Between the Local APIC and the 82489DX.”The APIC architecture used in the Pentium 4 and Intel Xeon processors (called thexAPIC architecture) is an extension of the APIC architecture found in the P6 familyprocessors. The primary difference between the APIC and xAPIC architectures is thatwith the xAPIC architecture, the local APICs and the I/O APIC communicate throughthe system bus. With the APIC architecture, they communication through the APICbus (see Section 8.2, “System Bus Vs.
APIC Bus”). Also, some APIC architecturalfeatures have been extended and/or modified in the xAPIC architecture. Theseextensions and modifications are noted in the following sections.Vol. 3 8-5ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)8.4LOCAL APICThe following sections describe the architecture of the local APIC and how to detectit, identify it, and determine its status.
Descriptions of how to program the local APICare given in Section 8.5.1, “Local Vector Table,” and Section 8.6.1, “InterruptCommand Register (ICR).”8.4.1The Local APIC Block DiagramFigure 8-4 gives a functional block diagram for the local APIC. Software interactswith the local APIC by reading and writing its registers. APIC registers are memorymapped to a 4-KByte region of the processor’s physical address space with an initialstarting address of FEE00000H. For correct APIC operation, this address space mustbe mapped to an area of memory that has been designated as strong uncacheable(UC). See Section 10.3, “Methods of Caching Available.”In MP system configurations, the APIC registers for Intel 64 or IA-32 processors onthe system bus are initially mapped to the same 4-KByte region of the physicaladdress space.
Software has the option of changing initial mapping to a different4-KByte region for all the local APICs or of mapping the APIC registers for each localAPIC to its own 4-KByte region. Section 8.4.5, “Relocating the Local APIC Registers,”describes how to relocate the base address for APIC registers.NOTEFor P6 family, Pentium 4, and Intel Xeon processors, the APIChandles all memory accesses to addresses within the 4-KByte APICregister space internally and no external bus cycles are produced.
Forthe Pentium processors with an on-chip APIC, bus cycles areproduced for accesses to the APIC register space. Thus, for softwareintended to run on Pentium processors, system software shouldexplicitly not map the APIC register space to regular system memory.Doing so can result in an invalid opcode exception (#UD) beinggenerated or unpredictable execution.8-6 Vol.
3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)DATA/ADDRVersion RegisterEOI RegisterTimerTask Priority RegisterCurrent CountRegisterInitial CountRegisterProcessor PriorityRegisterDivide ConfigurationRegisterPrioritizerINTAFromCPUCoreINTRToCPUCoreEXTINTLocal Vector TableTimerLINT0/1Perf. Mon.(InternalInterrupt)ThermalSensor(InternalInterrupt)LocalInterrupts 0,1In-Service Register (ISR)Interrupt Request Register (IRR)PerformanceMonitoring Counters1Trigger Mode Register (TMR)Thermal Sensor2ErrorVec[3:0]& TMR BitArb. IDRegister4Error StatusRegisterLocalInterruptsRegisterSelectVectorDecodeAcceptanceLogicDest. Mode& VectorProtocolTranslation LogicAPIC IDRegisterLogical DestinationRegisterDestination FormatRegisterToCPUCoreINITNMISMIInterrupt CommandRegister (ICR)Spurious VectorRegisterProcessor System Bus31.
Introduced in P6 family processors.2. Introduced in the Pentium 4 and Intel Xeon processors.3. Three-wire APIC bus in P6 family and Pentium processors.4. Not implemented in Pentium 4 and Intel Xeon processors.Figure 8-4. Local APIC StructureVol. 3 8-7ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Table 8-1 shows how the APIC registers are mapped into the 4-KByte APIC registerspace. Registers are 32 bits, 64 bits, or 256 bits in width; all are aligned on 128-bitboundaries. All 32-bit registers should be accessed using 128-bit aligned 32-bit loadsor stores. Some processors may support loads and stores of less than 32 bits to someof the APIC registers.
This is model specific behavior and is not guaranteed to workon all processors. Wider registers (64-bit or 256-bit) must be accessed using multiple32-bit loads or stores, with each access being 128-bit aligned.The local APIC registers listed in Table 8-1 are not MSRs. The only MSR associatedwith the programming of the local APIC is the IA32_APIC_BASE MSR (see Section8.4.3, “Enabling or Disabling the Local APIC”).Table 8-1. Local APIC Register Address MapAddressRegister NameSoftwareRead/WriteFEE0 0000HReservedFEE0 0010HReservedFEE0 0020HLocal APIC ID RegisterRead/Write.FEE0 0030HLocal APIC Version RegisterRead Only.FEE0 0040HReservedFEE0 0050HReservedFEE0 0060HReservedFEE0 0070HReservedFEE0 0080HTask Priority Register (TPR)Register1Read/Write.FEE0 0090HArbitration PriorityFEE0 00A0HProcessor Priority Register (PPR)Read Only.FEE0 00B0HEOI RegisterWrite Only.FEE0 00C0HReservedFEE0 00D0HLogical Destination RegisterRead/Write.FEE0 00E0HDestination Format RegisterBits 0-27 Read only;bits 28-31Read/Write.FEE0 00F0HSpurious Interrupt Vector RegisterBits 0-8 Read/Write;bits 9-31 Read Only.FEE0 0100HIn-Service Register (ISR); bits 0:31Read Only.FEE0 0110HIn-Service Register (ISR); bits 32:63Read Only.FEE0 0120HIn-Service Register (ISR); bits 64:95Read Only.FEE0 0130HIn-Service Register (ISR); bits 96:127Read Only.8-8 Vol.
3(APR)Read Only.ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Table 8-1. Local APIC Register Address Map (Contd.)AddressRegister NameSoftwareRead/WriteFEE0 0140HIn-Service Register (ISR); bits 128:159Read Only.FEE0 0150HIn-Service Register (ISR); bits 160:191Read Only.FEE0 0160HIn-Service Register (ISR); bits 192:223Read Only.FEE0 0170HIn-Service Register (ISR); bits 224:255Read Only.FEE0 0180HTrigger Mode Register (TMR); bits 0:31Read Only.FEE0 0180HTrigger Mode Register (TMR); bits 32:63Read Only.FEE0 01A0HTrigger Mode Register (TMR); bits 64:95Read Only.FEE0 01B0HTrigger Mode Register (TMR); bits 96:127Read Only.FEE0 01C0HTrigger Mode Register (TMR); bits 128:159Read Only.FEE0 01D0HTrigger Mode Register (TMR); bits 160:191Read Only.FEE0 01E0HTrigger Mode Register (TMR); bits 192:223Read Only.FEE0 01F0HTrigger Mode Register (TMR); bits 224:255Read Only.FEE0 0200HInterrupt Request Register (IRR); bits 0:31Read Only.FEE0 0210HInterrupt Request Register (IRR); bits32:63Read Only.FEE0 0220HInterrupt Request Register (IRR); bits 64:95Read Only.FEE0 0230HInterrupt Request Register (IRR); bits 96:127Read Only.FEE0 0240HInterrupt Request Register (IRR); bits 128:159 Read Only.FEE0 0250HInterrupt Request Register (IRR); bits 160:191 Read Only.FEE0 0260HInterrupt Request Register (IRR); bits 192:223 Read Only.FEE0 0270HInterrupt Request Register (IRR); bits 224:255 Read Only.FEE0 0280HError Status RegisterFEE0 0290H throughFEE0 02F0HReservedFEE0 0300HInterrupt Command Register (ICR); bits 0-31Read/Write.FEE0 0310HInterrupt Command Register (ICR); bits 32-63Read/Write.FEE0 0320HLVT Timer RegisterRead/Write.Register2Read Only.FEE0 0330HLVT Thermal SensorFEE0 0340HLVT Performance Monitoring CountersRegister3Read/Write.FEE0 0350HLVT LINT0 RegisterRead/Write.FEE0 0360HLVT LINT1 RegisterRead/Write.Read/Write.Vol.
3 8-9ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)Table 8-1. Local APIC Register Address Map (Contd.)AddressRegister NameSoftwareRead/WriteFEE0 0370HLVT Error RegisterRead/Write.FEE0 0380HInitial Count Register (for Timer)Read/Write.FEE0 0390HCurrent Count Register (for Timer)Read Only.FEE0 03A0H throughFEE0 03D0HReservedFEE0 03E0HDivide Configuration Register (for Timer)FEE0 03F0HReservedRead/Write.NOTES:1. Not supported in the Pentium 4 and Intel Xeon processors.2. Introduced in the Pentium 4 and Intel Xeon processors. This APIC register and its associatedfunction are implementation dependent and may not be present in future IA-32 or Intel 64 processors.3.
Introduced in the Pentium Pro processor. This APIC register and its associated function areimplementation dependent and may not be present in future IA-32 or Intel 64 processors.8.4.2Presence of the Local APICBeginning with the P6 family processors, the presence or absence of an on-chip localAPIC can be detected using the CPUID instruction. When the CPUID instruction isexecuted with a source operand of 1 in the EAX register, bit 9 of the CPUID featureflags returned in the EDX register indicates the presence (set) or absence (clear) of alocal APIC.8.4.3Enabling or Disabling the Local APICThe local APIC can be enabled or disabled in either of two ways:1.
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