Volume 3A System Programming Guide_ Part 1 (794103), страница 81
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The practice increases the chance thatthe processor’s caches will contain some of the thread’s code and data when it isdispatched for execution after being suspended.7.11.6.6Eliminate Execution-Based Timing LoopsIntel discourages the use of timing loops that depend on a processor’s executionspeed to measure time. There are several reasons:•Timing loops cause problems when they are calibrated on a IA-32 processorrunning at one clock speed and then executed on a processor running at anotherclock speed.•Routines for calibrating execution-based timing loops produce unpredictableresults when run on an IA-32 processor supporting Hyper-Threading Technology.This is due to the sharing of execution resources between the logical processorswithin a physical package.To avoid the problems described, timing loop routines must use a timing mechanismfor the loop that does not depend on the execution speed of the logical processors inthe system.
The following sources are generally available:••A high resolution system timer (for example, an Intel 8254).A high resolution timer within the processor (such as, the local APIC timer or thetime-stamp counter).For additional information, see the Intel® 64 and IA-32 Architectures OptimizationReference Manual.7.11.6.7Place Locks and Semaphores in Aligned, 128-Byte Blocks ofMemoryWhen software uses locks or semaphores to synchronize processes, threads, or othercode sections; Intel recommends that only one lock or semaphore be present withina cache line (or 128 byte sector, if 128-byte sector is supported).
In processors basedVol. 3 7-55MULTIPLE-PROCESSOR MANAGEMENTon Intel NetBurst microarchitecture (which support 128-byte sector consisting of twocache lines), following this recommendation means that each lock or semaphoreshould be contained in a 128-byte block of memory that begins on a 128-byteboundary. The practice minimizes the bus traffic required to service locks.7-56 Vol.
3CHAPTER 8ADVANCED PROGRAMMABLEINTERRUPT CONTROLLER (APIC)The Advanced Programmable Interrupt Controller (APIC), referred to in the followingsections as the local APIC, was introduced into the IA-32 processors with the Pentiumprocessor (see Section 17.26, “Advanced Programmable Interrupt Controller(APIC)”) and is included in the P6 family, Pentium 4, Intel Xeon processors, and othermore recent Intel 64 and IA-32 processor families (see Section 8.4.2, “Presence ofthe Local APIC”). The local APIC performs two primary functions for the processor:•It receives interrupts from the processor’s interrupt pins, from internal sourcesand from an external I/O APIC (or other external interrupt controller).
It sendsthese to the processor core for handling.•In multiple processor (MP) systems, it sends and receives interprocessorinterrupt (IPI) messages to and from other logical processors on the system bus.IPI messages can be used to distribute interrupts among the processors in thesystem or to execute system wide functions (such as, booting up processors ordistributing work among a group of processors).The external I/O APIC is part of Intel’s system chip set.
Its primary function is toreceive external interrupt events from the system and its associated I/O devices andrelay them to the local APIC as interrupt messages. In MP systems, the I/O APIC alsoprovides a mechanism for distributing external interrupts to the local APICs ofselected processors or groups of processors on the system bus.This chapter provides a description of the local APIC and its programming interface.It also provides an overview of the interface between the local APIC and the I/OAPIC. Contact Intel for detailed information about the I/O APIC.When a local APIC has sent an interrupt to its processor core for handling, theprocessor uses the interrupt and exception handling mechanism described in Chapter5, “Interrupt and Exception Handling.” See Section 5.1, “Interrupt and ExceptionOverview,” for an introduction to interrupt and exception handling.8.1LOCAL AND I/O APIC OVERVIEWEach local APIC consists of a set of APIC registers (see Table 8-1) and associatedhardware that control the delivery of interrupts to the processor core and the generation of IPI messages.
The APIC registers are memory mapped and can be read andwritten to using the MOV instruction.Local APICs can receive interrupts from the following sources:•Locally connected I/O devices — These interrupts originate as an edge orlevel asserted by an I/O device that is connected directly to the processor’s localVol.
3 8-1ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)interrupt pins (LINT0 and LINT1). The I/O devices may also be connected to an8259-type interrupt controller that is in turn connected to the processor throughone of the local interrupt pins.•Externally connected I/O devices — These interrupts originate as an edge orlevel asserted by an I/O device that is connected to the interrupt input pins of anI/O APIC. Interrupts are sent as I/O interrupt messages from the I/O APIC to oneor more of the processors in the system.•Inter-processor interrupts (IPIs) — An Intel 64 or IA-32 processor can usethe IPI mechanism to interrupt another processor or group of processors on thesystem bus.
IPIs are used for software self-interrupts, interrupt forwarding, orpreemptive scheduling.•APIC timer generated interrupts — The local APIC timer can be programmedto send a local interrupt to its associated processor when a programmed count isreached (see Section 8.5.4, “APIC Timer”).•Performance monitoring counter interrupts — P6 family, Pentium 4, andIntel Xeon processors provide the ability to send an interrupt to its associatedprocessor when a performance-monitoring counter overflows (see Section18.15.6.8, “Generating an Interrupt on Overflow”).•Thermal Sensor interrupts — Pentium 4 and Intel Xeon processors provide theability to send an interrupt to themselves when the internal thermal sensor hasbeen tripped (see Section 13.5.2, “Thermal Monitor”).•APIC internal error interrupts — When an error condition is recognized withinthe local APIC (such as an attempt to access an unimplemented register), theAPIC can be programmed to send an interrupt to its associated processor (seeSection 8.5.3, “Error Handling”).Of these interrupt sources: the processor’s LINT0 and LINT1 pins, the APIC timer, theperformance-monitoring counters, the thermal sensor, and the internal APIC errordetector are referred to as local interrupt sources.
Upon receiving a signal from alocal interrupt source, the local APIC delivers the interrupt to the processor coreusing an interrupt delivery protocol that has been set up through a group of APICregisters called the local vector table or LVT (see Section 8.5.1, “Local VectorTable”). A separate entry is provided in the local vector table for each local interruptsource, which allows a specific interrupt delivery protocol to be set up for eachsource.
For example, if the LINT1 pin is going to be used as an NMI pin, the LINT1entry in the local vector table can be set up to deliver an interrupt with vector number2 (NMI interrupt) to the processor core.The local APIC handles interrupts from the other two interrupt sources (externallyconnected I/O devices and IPIs) through its IPI message handling facilities.A processor can generate IPIs by programming the interrupt command register (ICR)in its local APIC (see Section 8.6.1, “Interrupt Command Register (ICR)”).
The act ofwriting to the ICR causes an IPI message to be generated and issued on the systembus (for Pentium 4 and Intel Xeon processors) or on the APIC bus (for Pentium andP6 family processors). See Section 8.2, “System Bus Vs. APIC Bus.”8-2 Vol. 3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)IPIs can be sent to other processors in the system or to the originating processor(self-interrupts).
When the target processor receives an IPI message, its local APIChandles the message automatically (using information included in the message suchas vector number and trigger mode). See Section 8.6, “Issuing Interprocessor Interrupts,” for a detailed explanation of the local APIC’s IPI message delivery and acceptance mechanism.The local APIC can also receive interrupts from externally connected devices throughthe I/O APIC (see Figure 8-1). The I/O APIC is responsible for receiving interruptsgenerated by system hardware and I/O devices and forwarding them to the localAPIC as interrupt messages.Pentium 4 andIntel Xeon ProcessorsPentium and P6Family ProcessorsProcessor CoreProcessor CoreLocal APICLocal APICInterruptMessagesInterruptMessagesLocalInterruptsInterruptMessages3-Wire APIC BusSystem BusBridgeI/O APICPCII/O APICLocalInterruptsExternalInterruptsSystem Chip SetExternalInterruptsSystem Chip SetFigure 8-1.
Relationship of Local APIC and I/O APIC In Single-Processor SystemsIndividual pins on the I/O APIC can be programmed to generate a specific interruptvector when asserted. The I/O APIC also has a “virtual wire mode” that allows it tocommunicate with a standard 8259A-style external interrupt controller. Note that thelocal APIC can be disabled (see Section 8.4.3, “Enabling or Disabling the LocalAPIC”). This allows an associated processor core to receive interrupts directly froman 8259A interrupt controller.Both the local APIC and the I/O APIC are designed to operate in MP systems (seeFigures 8-2 and 8-3). Each local APIC handles interrupts from the I/O APIC, IPIs fromprocessors on the system bus, and self-generated interrupts.
Interrupts can also beVol. 3 8-3ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)delivered to the individual processors through the local interrupt pins; however, thismechanism is commonly not used in MP systems.Processor #1Processor #2Processor #3Processor #3CPUCPUCPUCPULocal APICLocal APICLocal APICLocal APICInterruptMessagesIPIsInterruptMessagesIPIsInterruptMessagesIPIsInterruptMessagesIPIsProcessor System BusInterruptMessagesBridgePCIExternalInterruptsI/O APICSystem Chip SetFigure 8-2. Local APICs and I/O APIC When Intel Xeon Processors Are Used inMultiple-Processor SystemsProcessor #1Processor #2Processor #3Processor #4CPUCPUCPUCPULocal APICLocal APICLocal APICLocal APICInterruptMessagesIPIsInterruptMessagesIPIsInterruptMessagesInterruptMessagesExternalInterruptsIPIsInterruptMessagesIPIs3-wire APIC BusI/O APICSystem Chip SetFigure 8-3.
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