Volume 3A System Programming Guide_ Part 1 (794103), страница 77
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In the multi-processorsystems, typically bus and memory sub-systems are physically shared betweenmultiple sockets. Within a hardware multi-threading capable processors, certainresources are provided for each processor core, while other resources may beprovided for each logical processors (see Section 7.8, “Intel® Hyper-Threading Technology Architecture,” and Section 7.9, “Multi-Core Architecture”).From a software programming perspective, control transfer of processor operation ismanaged at the granularity of logical processor (operating systems dispatch arunnable task by allocating an available logical processor on the platform). Tomanage the topology of shared resources in a multi-threading environment, it isuseful for software to understand and manage resources that may be shared by morethan one logical processors.
This can be facilitated by mapping several levels of hierarchical labels to the initial APIC_ID of each logical processor to identify the topologyof shared resources.7.10.1Hierarchical Mapping of Shared ResourcesThe initial APIC_ID value associated with each logical processor in a multi-processorsystem is unique (see Section 7.7, “Detecting Hardware Multi-Threading Support andTopology”).
This 8-bit value can be decomposed into sub-fields, where each sub-fieldcorresponds a hierarchical level of the topological mapping of hardware resources.The decomposition of an initial APIC_ID may consist of 4 sub fields, matching 4 levelsof hierarchy:7-36 Vol. 3MULTIPLE-PROCESSOR MANAGEMENT•Cluster — Some multi-threading environments consists of multiple clusters ofmulti-processor systems. The CLUSTER_ID sub-field distinguishes differentclusters.
For non-clustered systems, CLUSTER_ID is usually 0.•Package — A multi-processor system consists of two or more sockets, eachmates with a physical processor package. The PACKAGE_ID sub-field distinguishes different physical packages within a cluster.•Core — A physical processor package consists of one or more processor cores.The CORE_ID sub-field distinguishes processor cores in a package. For a singlecore processor, the width of this bit field is 0.•SMT — A processor core provides one or more logical processors sharingexecution resources.
The SMT_ID sub-field distinguishes logical processors in acore. The width of this bit field is non-zero if a processor core provides more thanone logical processors.SMT and CORE sub-fields are bit-wise contiguous in the 8-bit APIC_ID field (seeFigure 7-5). The width of each sub-field depends on hardware and software configurations. Field widths can be determined at runtime using the algorithm discussedbelow (Example 7-1 through Example 7-3).
Figure 7-6 depicts the relationships ofthree of the hierarchical sub-fields in a hypothetical MP system.The value of valid APIC_IDs need not be contiguous across package boundary or coreboundaries.70ReservedCluster IDPackage IDCore IDSMT IDFigure 7-5. Generalized Four level Interpretation of the initial APIC ID7.10.2Identifying Logical Processors in an MP SystemFor Intel 64 and IA-32 processors, system hardware establishes an initial APIC IDthat is unique for each logical processor following power-up or RESET (see Section7.7.1). Each logical processor on the system is allocated an initial APIC ID. BIOS mayimplement features that tell the OS to support less than the total number of logicalprocessors on the system bus. Those logical processors that are not available toapplications at runtime are halted during the OS boot process.
As a result, thenumber valid local APIC_IDs that can be queried by affinitizing-current-threadcontext (See Example 7-3) is limited to the number of logical processors enabled atruntime by the OS boot process.Vol. 3 7-37MULTIPLE-PROCESSOR MANAGEMENTTable 7-1 shows the APIC IDs that are initially reported for logical processors in asystem with four Intel Xeon MP processors that support Hyper-Threading Technology(a total of 8 logical processors, each physical package has two processor cores andsupports Hyper-Threading Technology). Of the two logical processors within a IntelXeon processor MP, logical processor 0 is designated the primary logical processorand logical processor 1 as the secondary logical processor.T0T1Core 0T0T1T0Core1T1Core 0T0Core1Package 1Package 0T1SMT_IDCore IDPackage IDFigure 7-6.
Topological Relationships between Hierarchical IDs in a Hypothetical MPPlatformTable 7-1. Initial APIC IDs for the Logical Processors in a System that has Four IntelXeon MP Processors Supporting Hyper-Threading Technology1Initial APIC ID of LogicalProcessorPackage IDCore IDSMT ID0H0H0H0H1H0H0H1H2H1H0H0H3H1H0H1H4H2H0H0H5H2H0H1H6H3H0H0H7H3H0H1HNOTE:1. Because information on the number of processor cores in a physical package was not availablein early single-core processors supporting Hyper-Threading Technology, the core ID can betreated as 0.7-38 Vol. 3MULTIPLE-PROCESSOR MANAGEMENTTable 7-2 shows the initial APIC IDs for a hypothetical situation with a dual processorsystem.
Each physical package providing two processor cores, and each processorcore also supporting Hyper-Threading Technology.Table 7-2. Initial APIC IDs for the Logical Processors in a System that has TwoPhysical Processors Supporting Dual-Core and Hyper-Threading TechnologyInitial APIC ID of a LogicalProcessorPackage IDCore IDSMT ID0H0H0H0H1H0H0H1H2H0H1H0H3H0H1H1H4H1H0H0H5H1H0H1H6H1H1H0H7H1H1H1H7.10.3Algorithm for Three-Level Mappings of APIC_IDSoftware can gather the initial APIC_IDs for each logical processor supported by theoperating system at runtime5 and extract identifiers corresponding to the threelevels of sharing topology (package, core, and SMT). The algorithms below focus ona non-clustered MP system for simplicity. They do not assume initial APIC_IDs arecontiguous or that all logical processors on the platform are enabled.Intel supports multi-threading systems where all physical processors report identicalvalues in CPUID.1:EBX[23:16]), CPUID.46:EAX[31:26], and CPUID.47:EAX[25:14].The algorithms below assume the target system has symmetry across physicalpackage boundaries with respect to the number of logical processors per package,number of cores per package, and cache topology within a package.The extraction algorithm (for three-level mappings of an initial APIC_ID) uses thefollowing support routines (Example 7-1):1.
Detect capability for hardware multi-threading support in the processor.5. As noted in Section 7.7 and Section 7.10.2, the number of logical processors supported by theOS at runtime may be less than the total number logical processors available in the platformhardware.6. Maximum number of cores per physical processor is obtained by executing CPUID with EAX=4and a valid ECX index, The ECX index start at 0.7. Maximum number of cores sharing the target cache level is obtained by executing CPUID withEAX = 4 and the ECX index corresponding to the target cache level.Vol.
3 7-39MULTIPLE-PROCESSOR MANAGEMENT2. Identify the maximum number of logical processors in a physical processorpackage. This is used to determine the topological relationship between logicalprocessors and the physical package.3. Identify the maximum number of processor cores in a physical processorpackage. This is used to determine the topological relationship betweenprocessor cores and the physical package.4. Extract the initial APIC ID for the logical processor where the current thread isexecuting.5. Calculate a mask from the maximum count that the bit field can represent.6.
Use full 8-bit ID and mask to extract sub-field IDs.Example 7-1. Support Routines for Detecting Hardware Multi-Threading and Identifying theRelationships Between Package, Core and Logical Processors1.//////////Detect support for Hardware Multi-Threading Support in a processor.Returns a non-zero value if CPUID reports the presence of hardware multi-threadingsupport in the physical package where the current logical processor is located.This does not guarantee BIOS or OS will enable all logical processors in the physicalpackage and make them available to applications.Returns zero if hardware multi-threading is not present.#define HWMT_BIT 0x10000000unsigned int HWMTSupported(void){// ensure cpuid instruction is supportedexecute cpuid with eax = 0 to get vendor stringexecute cpuid with eax = 1 to get feature flag and signature// Check to see if this a Genuine Intel Processorif (vendor string EQ GenuineIntel) {return (feature_flag_edx & HWMT_BIT); // bit 28}return 0;}2.Find the Max number of logical processors per physical processor package.#define NUM_LOGICAL_BITS 0x00FF0000// Use the mask above and CPUID.1.EBX[23:16] to obtain the max number of logical processors// per package,7-40 Vol.
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