Volume 3A System Programming Guide_ Part 1 (794103), страница 73
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They leave their BSP flags in the clear stateand enter a “wait-for-SIPI state.”— Family, model, and stepping IDs up to F09H:•Each processor broadcasts a BIPI to “all including self.” The first processorthat broadcasts a BIPI (and thus receives its own BIPI vector), selectsitself as the BSP and sets the BSP flag in its IA32_APIC_BASE MSR. (SeeAppendix C.1, “Overview of the MP Initialization Process For P6 FamilyProcessors,” for a description of the BIPI, FIPI, and SIPI messages.)•The remainder of the processors (which were not selected as the BSP) aredesignated as APs. They leave their BSP flags in the clear state and entera “wait-for-SIPI state.”•The newly established BSP broadcasts an FIPI message to “all includingself,” which the BSP and APs treat as an end of MP initialization signal.Only the processor with its BSP flag set responds to the FIPI message. Itresponds by fetching and executing the BIOS boot-strap code, beginningat the reset vector (physical address FFFF FFF0H).5.
As part of the boot-strap code, the BSP creates an ACPI table and an MP table andadds its initial APIC ID to these tables as appropriate.6. At the end of the boot-strap procedure, the BSP sets a processor counter to 1,then broadcasts a SIPI message to all the APs in the system. Here, the SIPImessage contains a vector to the BIOS AP initialization code (at 000VV000H,where VV is the vector contained in the SIPI message).7. The first action of the AP initialization code is to set up a race (among the APs) toa BIOS initialization semaphore. The first AP to the semaphore begins executingthe initialization code. (See Section 7.5.4, “MP Initialization Example,” forsemaphore implementation details.) As part of the AP initialization procedure,the AP adds its APIC ID number to the ACPI and MP tables as appropriate and7-18 Vol.
3MULTIPLE-PROCESSOR MANAGEMENTincrements the processor counter by 1. At the completion of the initializationprocedure, the AP executes a CLI instruction and halts itself.8. When each of the APs has gained access to the semaphore and executed the APinitialization code, the BSP establishes a count for the number of processorsconnected to the system bus, completes executing the BIOS boot-strap code,and then begins executing operating-system boot-strap and start-up code.9. While the BSP is executing operating-system boot-strap and start-up code, theAPs remain in the halted state.
In this state they will respond only to INITs, NMIs,and SMIs. They will also respond to snoops and to assertions of the STPCLK# pin.The following section gives an example (with code) of the MP initialization protocolfor multiple Intel Xeon processors operating in an MP configuration.Appendix B, “Model-Specific Registers (MSRs),” describes how to program theLINT[0:1] pins of the processor’s local APICs after an MP configuration has beencompleted.7.5.4MP Initialization ExampleThe following example illustrates the use of the MP initialization protocol used toinitialize processors in an MP system after the BSP and APs have been established.The code runs on Intel 64 or IA-32 processors that use a protocol.
This includes P6Family processors, Pentium 4 processors, Intel Core Duo, Intel Core 2 Duo and IntelXeon processors.The following constants and data definitions are used in the accompanying codeexamples. They are based on the addresses of the APIC registers defined in Table8-1.ICR_LOWSVRAPIC_IDLVT3APIC_ENABLEDBOOT_IDCOUNTVACANT7.5.4.1EQU 0FEE00300HEQU 0FEE000F0HEQU 0FEE00020HEQU 0FEE00370HEQU 0100HDD ?EQU 00HEQU 00HTypical BSP Initialization SequenceAfter the BSP and APs have been selected (by means of a hardware protocol, seeSection 7.5.3, “MP Initialization Protocol Algorithm for Intel Xeon Processors”), theBSP begins executing BIOS boot-strap code (POST) at the normal IA-32 architecturestarting address (FFFF FFF0H). The boot-strap code typically performs the followingoperations:1.
Initializes memory.Vol. 3 7-19MULTIPLE-PROCESSOR MANAGEMENT2. Loads the microcode update into the processor.3. Initializes the MTRRs.4. Enables the caches.5. Executes the CPUID instruction with a value of 0H in the EAX register, then readsthe EBX, ECX, and EDX registers to determine if the BSP is “GenuineIntel.”6. Executes the CPUID instruction with a value of 1H in the EAX register, then savesthe values in the EAX, ECX, and EDX registers in a system configuration space inRAM for use later.7. Loads start-up code for the AP to execute into a 4-KByte page in the lower 1MByte of memory.8. Switches to protected mode and insures that the APIC address space is mappedto the strong uncacheable (UC) memory type.9.
Determine the BSP’s APIC ID from the local APIC ID register (default is 0):MOV ESI, APIC_ID; Address of local APIC ID registerMOV EAX, [ESI];AND EAX, 0FF000000H; Zero out all other bits except APIC IDMOV BOOT_ID, EAX; Save in memorySaves the APIC ID in the ACPI and MP tables and optionally in the system configuration space in RAM.10. Converts the base address of the 4-KByte page for the AP’s bootup code into 8-bitvector.
The 8-bit vector defines the address of a 4-KByte page in the real-addressmode address space (1-MByte space). For example, a vector of 0BDH specifies astart-up memory address of 000BD000H.11. Enables the local APIC by setting bit 8 of the APIC spurious vector register (SVR).MOV ESI, SVR; Address of SVRMOV EAX, [ESI];OR EAX, APIC_ENABLED; Set bit 8 to enable (0 on reset)MOV [ESI], EAX;12. Sets up the LVT error handling entry by establishing an 8-bit vector for the APICerror handler.MOV ESI, LVT3;MOV EAX, [ESI];AND EAX, FFFFFF00H; Clear out previous vector.OR EAX, 000000xxH; xx is the 8-bit vector the APIC error handler.MOV [ESI], EAX;13.
Initializes the Lock Semaphore variable VACANT to 00H. The APs use thissemaphore to determine the order in which they execute BIOS AP initializationcode.7-20 Vol. 3MULTIPLE-PROCESSOR MANAGEMENT14. Performs the following operation to set up the BSP to detect the presence of APsin the system and the number of processors:— Sets the value of the COUNT variable to 1.— Starts a timer (set for an approximate interval of 100 milliseconds). In the APBIOS initialization code, the AP will increment the COUNT variable to indicateits presence. When the timer expires, the BSP checks the value of the COUNTvariable. If the timer expires and the COUNT variable has not been incremented, no APs are present or some error has occurred.15.
Broadcasts an INIT-SIPI-SIPI IPI sequence to the APs to wake them up andinitialize them:MOV ESI, ICR_LOW; Load address of ICR low dword into ESI.MOV EAX, 000C4500H; Load ICR encoding for broadcast INIT IPI; to all APs into EAX.MOV [ESI], EAX; Broadcast INIT IPI to all APs; 10-millisecond delay loop.MOV EAX, 000C46XXH; Load ICR encoding for broadcast SIPI IP; to all APs into EAX, where xx is the vector computed in step 10.MOV [ESI], EAX; Broadcast SIPI IPI to all APs; 200-microsecond delay loopMOV [ESI], EAX; Broadcast second SIPI IPI to all APs; 200-microsecond delay loopStep 15:MOV EAX, 000C46XXH; Load ICR encoding from broadcast SIPI IP; to all APs into EAX where xx is the vector computed in step 8.16. Waits for the timer interrupt.17. Reads and evaluates the COUNT variable and establishes a processor count.18. If necessary, reconfigures the APIC and continues with the remaining systemdiagnostics as appropriate.7.5.4.2Typical AP Initialization SequenceWhen an AP receives the SIPI, it begins executing BIOS AP initialization code at thevector encoded in the SIPI.
The AP initialization code typically performs the followingoperations:1. Waits on the BIOS initialization Lock Semaphore. When control of the semaphoreis attained, initialization continues.2. Loads the microcode update into the processor.3. Initializes the MTRRs (using the same mapping that was used for the BSP).4. Enables the cache.Vol. 3 7-21MULTIPLE-PROCESSOR MANAGEMENT5. Executes the CPUID instruction with a value of 0H in the EAX register, then readsthe EBX, ECX, and EDX registers to determine if the AP is “GenuineIntel.”6. Executes the CPUID instruction with a value of 1H in the EAX register, then savesthe values in the EAX, ECX, and EDX registers in a system configuration space inRAM for use later.7.
Switches to protected mode and insures that the APIC address space is mappedto the strong uncacheable (UC) memory type.8. Determines the AP’s APIC ID from the local APIC ID register, and adds it to the MPand ACPI tables and optionally to the system configuration space in RAM.9. Initializes and configures the local APIC by setting bit 8 in the SVR register andsetting up the LVT3 (error LVT) for error handling (as described in steps 9 and 10in Section 7.5.4.1, “Typical BSP Initialization Sequence”).10. Configures the APs SMI execution environment.
(Each AP and the BSP must havea different SMBASE address.)11. Increments the COUNT variable by 1.12. Releases the semaphore.13. Executes the CLI and HLT instructions.14. Waits for an INIT IPI.7.5.5Identifying Logical Processors in an MP SystemAfter the BIOS has completed the MP initialization protocol, each logical processorcan be uniquely identified by its local APIC ID. Software can access these APIC IDs ineither of the following ways:•Read APIC ID for a local APIC — Code running on a logical processor canexecute a MOV instruction to read the processor’s local APIC ID register (seeSection 8.4.6, “Local APIC ID”). This is the ID to use for directing physicaldestination mode interrupts to the processor.•Read ACPI or MP table — As part of the MP initialization protocol, the BIOScreates an ACPI table and an MP table.
These tables are defined in the Multiprocessor Specification Version 1.4 and provide software with a list of the processorsin the system and their local APIC IDs. The format of the ACPI table is derivedfrom the ACPI specification, which is an industry standard power managementand platform configuration specification for MP systems.•Read Initial APIC ID — An APIC ID is assigned to a logical processor duringpower up and is called the initial APIC ID.
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