Volume 3A System Programming Guide_ Part 1 (794103), страница 68
Текст из файла (страница 68)
Thismapping is required so that the mapping of TSS addresses does not change while theprocessor is reading and updating the TSSs during a task switch. The linear addressspace mapped by the GDT also should be mapped to a shared area of the physicalspace; otherwise, the purpose of the GDT is defeated. Figure 6-9 shows how thelinear address spaces of two tasks can overlap in the physical space by sharing pagetables.TSSPage DirectoriesPage TablesPage FramesTask ATask A TSSPDBRPDEPDEPTEPTEPTETask ATask AShared PTSharedPTEPTETask B TSSSharedTask BPDBRPDEPDEPTEPTETask BFigure 6-9. Overlapping Linear-to-Physical Mappings6.5.2Task Logical Address SpaceTo allow the sharing of data among tasks, use the following techniques to createshared logical-to-physical address-space mappings for data segments:•Through the segment descriptors in the GDT — All tasks must have accessto the segment descriptors in the GDT.
If some segment descriptors in the GDTpoint to segments in the linear-address space that are mapped into an area of thephysical-address space common to all tasks, then all tasks can share the dataand code in those segments.•Through a shared LDT — Two or more tasks can use the same LDT if the LDTfields in their TSSs point to the same LDT.
If some segment descriptors in a6-20 Vol. 3TASK MANAGEMENTshared LDT point to segments that are mapped to a common area of the physicaladdress space, the data and code in those segments can be shared among thetasks that share the LDT. This method of sharing is more selective than sharingthrough the GDT, because the sharing can be limited to specific tasks.
Othertasks in the system may have different LDTs that do not give them access to theshared segments.•Through segment descriptors in distinct LDTs that are mapped tocommon addresses in linear address space — If this common area of thelinear address space is mapped to the same area of the physical address spacefor each task, these segment descriptors permit the tasks to share segments.Such segment descriptors are commonly called aliases. This method of sharing iseven more selective than those listed above, because, other segment descriptorsin the LDTs may point to independent linear addresses which are not shared.6.616-BIT TASK-STATE SEGMENT (TSS)The 32-bit IA-32 processors also recognize a 16-bit TSS format like the one used inIntel 286 processors (see Figure 6-10).
This format is supported for compatibilitywith software written to run on earlier IA-32 processors.The following information is important to know about the 16-bit TSS.•••Do not use a 16-bit TSS to implement a virtual-8086 task.•The I/O base address is not included in the 16-bit TSS. None of the functions ofthe I/O map are supported.•When task state is saved in a 16-bit TSS, the upper 16 bits of the EFLAGS registerand the EIP register are lost.•When the general-purpose registers are loaded or saved from a 16-bit TSS, theupper 16 bits of the registers are modified and not maintained.The valid segment limit for a 16-bit TSS is 2CH.The 16-bit TSS does not contain a field for the base address of the page directory,which is loaded into control register CR3.
A separate set of page tables for eachtask is not supported for 16-bit tasks. If a 16-bit task is dispatched, the pagetable structure for the previous task is used.Vol. 3 6-21TASK MANAGEMENT150Task LDT Selector42DS Selector40SS Selector38CS SelectorES Selector3634DI32SI30BP28SP26BX24DX22CX20AX18FLAG Word16IP (Entry Point)14SS212SP210SS18SP16SS04SP02Previous Task Link0Figure 6-10. 16-Bit TSS Format6.7TASK MANAGEMENT IN 64-BIT MODEIn 64-bit mode, task structure and task state are similar to those in protected mode.However, the task switching mechanism available in protected mode is not supportedin 64-bit mode.
Task management and switching must be performed by software.The processor issues a general-protection exception (#GP) if the following isattempted in 64-bit mode:••Control transfer to a TSS or a task gate using JMP, CALL, INTn, or interrupt.An IRET with EFLAGS.NT (nested task) set to 1.6-22 Vol. 3TASK MANAGEMENTAlthough hardware task-switching is not supported in 64-bit mode, a 64-bit taskstate segment (TSS) must exist.
Figure 6-11 shows the format of a 64-bit TSS. TheTSS holds information important to 64-bit mode and that is not directly related to thetask-switch mechanism. This information includes:•RSPn — The full 64-bit canonical forms of the stack pointers (RSP) for privilegelevels 0-2.••ISTn — The full 64-bit canonical forms of the interrupt stack table (IST) pointers.I/O map base address — The 16-bit offset to the I/O permission bit map fromthe 64-bit TSS base.The operating system must create at least one 64-bit TSS after activating IA-32emode.
It must execute the LTR instruction (in 64-bit mode) to load the TR registerwith a pointer to the 64-bit TSS responsible for both 64-bit-mode programs andcompatibility-mode programs.Vol. 3 6-23TASK MANAGEMENT31015ReservedI/O Map Base AddressReserved96Reserved92IST7 (upper 32 bits)88IST7 (lower 32 bits)84IST6 (upper 32 bits)80IST6 (lower 32 bits)76IST5 (upper 32 bits)72IST5 (lower 32 bits)68IST4 (upper 32 bits)64IST4 (lower 32 bits)60IST3 (upper 32 bits)56IST3 (lower 32 bits)52IST2 (upper 32 bits)48IST2 (lower 32 bits)44IST1 (upper 32 bits)40IST1 (lower 32 bits)36Reserved32Reserved28RSP2 (upper 32 bits)24RSP2 (lower 32 bits)20RSP1 (upper 32 bits)16RSP1 (lower 32 bits)12RSP0 (upper 32 bits)8RSP0 (lower 32 bits)4Reserved0Reserved bits.
Set to 0.Figure 6-11. 64-Bit TSS Format6-24 Vol. 3100CHAPTER 7MULTIPLE-PROCESSOR MANAGEMENTThe Intel 64 and IA-32 architectures provide mechanisms for managing andimproving the performance of multiple processors connected to the same systembus. These include:•Bus locking and/or cache coherency management for performing atomicoperations on system memory.•Serializing instructions.
These instructions apply only to the Pentium 4, IntelXeon, P6 family, and Pentium processors.•An advance programmable interrupt controller (APIC) located on the processorchip (see Chapter 8, “Advanced Programmable Interrupt Controller (APIC)”). Thisfeature was introduced by the Pentium processor.•A second-level cache (level 2, L2). For the Pentium 4, Intel Xeon, and P6 familyprocessors, the L2 cache is included in the processor package and is tightlycoupled to the processor. For the Pentium and Intel486 processors, pins areprovided to support an external L2 cache.•A third-level cache (level 3, L3). For Intel Xeon processors, the L3 cache isincluded in the processor package and is tightly coupled to the processor.•Hyper-Threading Technology.
This extension to the Intel 64 and IA-32 architectures enables a single processor core to execute two or more threads concurrently (see Section 7.6, “Hyper-Threading and Multi-Core Technology”).These mechanisms are particularly useful in symmetric-multiprocessing (SMP)systems. However, they can also be used when an Intel 64 or IA-32 processor and aspecial-purpose processor (such as a communications, graphics, or video processor)share the system bus.These multiprocessing mechanisms have the following characteristics:•To maintain system memory coherency — When two or more processors areattempting simultaneously to access the same address in system memory, somecommunication mechanism or memory access protocol must be available topromote data coherency and, in some instances, to allow one processor totemporarily lock a memory location.•To maintain cache consistency — When one processor accesses data cached onanother processor, it must not receive incorrect data.
If it modifies data, all otherprocessors that access that data must receive the modified data.•To allow predictable ordering of writes to memory — In some circumstances, it isimportant that memory writes be observed externally in precisely the same orderas programmed.•To distribute interrupt handling among a group of processors — When severalprocessors are operating in a system in parallel, it is useful to have a centralizedVol.
3 7-1MULTIPLE-PROCESSOR MANAGEMENTmechanism for receiving interrupts and distributing them to available processorsfor servicing.•To increase system performance by exploiting the multi-threaded and multiprocess nature of contemporary operating systems and applications.The caching mechanism and cache consistency of Intel 64 and IA-32 processors arediscussed in Chapter 10. The APIC architecture is described in Chapter 8.
Bus andmemory locking, serializing instructions, memory ordering, and Hyper-ThreadingTechnology are discussed in the following sections.7.1LOCKED ATOMIC OPERATIONSThe 32-bit IA-32 processors support locked atomic operations on locations in systemmemory. These operations are typically used to manage shared data structures (suchas semaphores, segment descriptors, system segments, or page tables) in which twoor more processors may try simultaneously to modify the same field or flag.
Theprocessor uses three interdependent mechanisms for carrying out locked atomicoperations:•••Guaranteed atomic operationsBus locking, using the LOCK# signal and the LOCK instruction prefixCache coherency protocols that insure that atomic operations can be carried outon cached data structures (cache lock); this mechanism is present in thePentium 4, Intel Xeon, and P6 family processorsThese mechanisms are interdependent in the following ways.
Certain basic memorytransactions (such as reading or writing a byte in system memory) are always guaranteed to be handled atomically. That is, once started, the processor guarantees thatthe operation will be completed before another processor or bus agent is allowedaccess to the memory location. The processor also supports bus locking forperforming selected memory operations (such as a read-modify-write operation in ashared area of memory) that typically need to be handled atomically, but are notautomatically handled this way. Because frequently used memory locations are oftencached in a processor’s L1 or L2 caches, atomic operations can often be carried outinside a processor’s caches without asserting the bus lock.
Here the processor’scache coherency protocols insure that other processors that are caching the samememory locations are managed properly while atomic operations are performed oncached memory locations.NOTEWhere there are contested lock accesses, software may need toimplement algorithms that ensure fair access to resources in order toprevent lock starvation.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
