Volume 3A System Programming Guide_ Part 1 (794103), страница 63
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Alignment checks are only carried out in data (or stack)accesses (not in code fetches or system segment accesses). An example of an alignment-check violation is a word stored at an odd byte address, or a doubleword storedat an address that is not an integer multiple of 4. Table 5-7 lists the alignmentrequirements various data types recognized by the processor.Table 5-7.
Alignment Requirements by Data TypeData TypeAddress Must Be Divisible ByWord2Doubleword4Single-precision floating-point (32-bits)4Double-precision floating-point (64-bits)8Double extended-precision floating-point (80bits)8Quadword8Double quadword16Segment Selector232-bit Far Pointer248-bit Far Pointer432-bit Pointer4GDTR, IDTR, LDTR, or Task Register Contents4FSTENV/FLDENV Save Area4 or 2, depending on operand sizeFSAVE/FRSTOR Save Area4 or 2, depending on operand sizeBit String2 or 4 depending on the operand-size attribute.Note that the alignment check exception (#AC) is generated only for data types thatmust be aligned on word, doubleword, and quadword boundaries. A general-protection exception (#GP) is generated 128-bit data types that are not aligned on a16-byte boundary.To enable alignment checking, the following conditions must be true:•AM flag in CR0 register is set.5-60 Vol.
3INTERRUPT AND EXCEPTION HANDLING••AC flag in the EFLAGS register is set.The CPL is 3 (protected mode or virtual-8086 mode).Alignment-check exceptions (#AC) are generated only when operating at privilegelevel 3 (user mode). Memory references that default to privilege level 0, such assegment descriptor loads, do not generate alignment-check exceptions, even whencaused by a memory reference made from privilege level 3.Storing the contents of the GDTR, IDTR, LDTR, or task register in memory while atprivilege level 3 can generate an alignment-check exception. Although applicationprograms do not normally store these registers, the fault can be avoided by aligningthe information stored on an even word-address.The FXSAVE and FXRSTOR instructions save and restore a 512-byte data structure,the first byte of which must be aligned on a 16-byte boundary.
If the alignment-checkexception (#AC) is enabled when executing these instructions (and CPL is 3), amisaligned memory operand can cause either an alignment-check exception or ageneral-protection exception (#GP) depending on the processor implementation(see “FXSAVE-Save x87 FPU, MMX, SSE, and SSE2 State” and “FXRSTOR-Restorex87 FPU, MMX, SSE, and SSE2 State” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).The MOVUPS and MOVUPD instructions perform 128-bit unaligned loads or stores.They do not generate general-protection exceptions (#GP) when operands are notaligned on a 16-byte boundary. If alignment checking is enabled, alignment-checkexceptions (#AC) are generated when instructions are not aligned on an 8-byteboundary.FSAVE and FRSTOR instructions can generate unaligned references, which can causealignment-check faults.
These instructions are rarely needed by applicationprograms.Exception Error CodeYes (always zero).Saved Instruction PointerThe saved contents of CS and EIP registers point to the instruction that generated theexception.Program State ChangeA program-state change does not accompany an alignment-check fault, because theinstruction is not executed.Vol. 3 5-61INTERRUPT AND EXCEPTION HANDLINGInterrupt 18—Machine-Check Exception (#MC)Exception ClassAbort.DescriptionIndicates that the processor detected an internal machine error or a bus error, or thatan external agent detected a bus error.
The machine-check exception is modelspecific, available only on the Pentium 4, Intel Xeon, P6 family, and Pentium processors. The implementation of the machine-check exception is different between thePentium 4, Intel Xeon, P6 family, and Pentium processors, and these implementations may not be compatible with future Intel 64 or IA-32 processors. (Use the CPUIDinstruction to determine whether this feature is present.)Bus errors detected by external agents are signaled to the processor on dedicatedpins: the BINIT# and MCERR# pins on the Pentium 4, Intel Xeon, and P6 familyprocessors and the BUSCHK# pin on the Pentium processor.
When one of these pinsis enabled, asserting the pin causes error information to be loaded into machinecheck registers and a machine-check exception is generated.The machine-check exception and machine-check architecture are discussed in detailin Chapter 14, “Machine-Check Architecture.” Also, see the data books for the individual processors for processor-specific hardware information.Exception Error CodeNone. Error information is provide by machine-check MSRs.Saved Instruction PointerFor the Pentium 4 and Intel Xeon processors, the saved contents of extendedmachine-check state registers are directly associated with the error that caused themachine-check exception to be generated (see Section 14.3.1.2,“IA32_MCG_STATUS MSR,” and Section 14.3.2.5, “IA32_MCG Extended MachineCheck State MSRs”).For the P6 family processors, if the EIPV flag in the MCG_STATUS MSR is set, thesaved contents of CS and EIP registers are directly associated with the error thatcaused the machine-check exception to be generated; if the flag is clear, the savedinstruction pointer may not be associated with the error (see Section 14.3.1.2,“IA32_MCG_STATUS MSR”).For the Pentium processor, contents of the CS and EIP registers may not be associated with the error.Program State ChangeThe machine-check mechanism is enabled by setting the MCE flag in control registerCR4.5-62 Vol.
3INTERRUPT AND EXCEPTION HANDLINGFor the Pentium 4, Intel Xeon, P6 family, and Pentium processors, a program-statechange always accompanies a machine-check exception, and an abort class exception is generated. For abort exceptions, information about the exception can becollected from the machine-check MSRs, but the program cannot generally berestarted.If the machine-check mechanism is not enabled (the MCE flag in control register CR4is clear), a machine-check exception causes the processor to enter the shutdownstate.Vol. 3 5-63INTERRUPT AND EXCEPTION HANDLINGInterrupt 19—SIMD Floating-Point Exception (#XF)Exception ClassFault.DescriptionIndicates the processor has detected an SSE/SSE2/SSE3 SIMD floating-point exception. The appropriate status flag in the MXCSR register must be set and the particularexception unmasked for this interrupt to be generated.There are six classes of numeric exception conditions that can occur while executingan SSE/ SSE2/SSE3 SIMD floating-point instruction:••••••Invalid operation (#I)Divide-by-zero (#Z)Denormal operand (#D)Numeric overflow (#O)Numeric underflow (#U)Inexact result (Precision) (#P)The invalid operation, divide-by-zero, and denormal-operand exceptions are precomputation exceptions; that is, they are detected before any arithmetic operationoccurs.
The numeric underflow, numeric overflow, and inexact result exceptions arepost-computational exceptions.See "SIMD Floating-Point Exceptions" in Chapter 11 of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for additional informationabout the SIMD floating-point exception classes.When a SIMD floating-point exception occurs, the processor does either of thefollowing things:•It handles the exception automatically by producing the most reasonable resultand allowing program execution to continue undisturbed.
This is the response tomasked exceptions.•It generates a SIMD floating-point exception, which in turn invokes a softwareexception handler. This is the response to unmasked exceptions.Each of the six SIMD floating-point exception conditions has a corresponding flag bitand mask bit in the MXCSR register. If an exception is masked (the correspondingmask bit in the MXCSR register is set), the processor takes an appropriate automaticdefault action and continues with the computation.
If the exception is unmasked (thecorresponding mask bit is clear) and the operating system supports SIMD floatingpoint exceptions (the OSXMMEXCPT flag in control register CR4 is set), a softwareexception handler is invoked through a SIMD floating-point exception. If the exception is unmasked and the OSXMMEXCPT bit is clear (indicating that the operatingsystem does not support unmasked SIMD floating-point exceptions), an invalidopcode exception (#UD) is signaled instead of a SIMD floating-point exception.5-64 Vol. 3INTERRUPT AND EXCEPTION HANDLINGNote that because SIMD floating-point exceptions are precise and occur immediately,the situation does not arise where an x87 FPU instruction, a WAIT/FWAIT instruction,or another SSE/SSE2/SSE3 instruction will catch a pending unmasked SIMD floatingpoint exception.In situations where a SIMD floating-point exception occurred while the SIMDfloating-point exceptions were masked (causing the corresponding exception flag tobe set) and the SIMD floating-point exception was subsequently unmasked, then noexception is generated when the exception is unmasked.When SSE/SSE2/SSE3 SIMD floating-point instructions operate on packed operands(made up of two or four sub-operands), multiple SIMD floating-point exceptionconditions may be detected.
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