Volume 3A System Programming Guide_ Part 1 (794103), страница 64
Текст из файла (страница 64)
If no more than one exception condition is detected forone or more sets of sub-operands, the exception flags are set for each exceptioncondition detected. For example, an invalid exception detected for one sub-operandwill not prevent the reporting of a divide-by-zero exception for another sub-operand.However, when two or more exceptions conditions are generated for one suboperand, only one exception condition is reported, according to the precedencesshown in Table 5-8.
This exception precedence sometimes results in the higherpriority exception condition being reported and the lower priority exception conditions being ignored.Table 5-8. SIMD Floating-Point Exceptions PriorityPriorityDescription1 (Highest)Invalid operation exception due to SNaN operand (or any NaN operand formaximum, minimum, or certain compare and convert operations).2QNaN operand1.3Any other invalid operation exception not mentioned above or a divide-by-zeroexception2.4Denormal operand exception2.5Numeric overflow and underflow exceptions possibly in conjunction with theinexact result exception2.6 (Lowest)Inexact result exception.NOTES:1. Though a QNaN this is not an exception, the handling of a QNaN operand has precedence overlower priority exceptions.
For example, a QNaN divided by zero results in a QNaN, not a divideby-zero- exception.2. If masked, then instruction execution continues, and a lower priority exception can occur aswell.Exception Error CodeNone.Vol. 3 5-65INTERRUPT AND EXCEPTION HANDLINGSaved Instruction PointerThe saved contents of CS and EIP registers point to the SSE/SSE2/SSE3 instructionthat was executed when the SIMD floating-point exception was generated. This is thefaulting instruction in which the error condition was detected.Program State ChangeA program-state change does not accompany a SIMD floating-point exceptionbecause the handling of the exception is immediate unless the particular exception ismasked. The available state information is often sufficient to allow recovery from theerror and re-execution of the faulting instruction if needed.5-66 Vol.
3INTERRUPT AND EXCEPTION HANDLINGInterrupts 32 to 255—User Defined InterruptsException ClassNot applicable.DescriptionIndicates that the processor did one of the following things:•Executed an INT n instruction where the instruction operand is one of the vectornumbers from 32 through 255.•Responded to an interrupt request at the INTR pin or from the local APIC whenthe interrupt vector number associated with the request is from 32 through 255.Exception Error CodeNot applicable.Saved Instruction PointerThe saved contents of CS and EIP registers point to the instruction that follows theINT n instruction or instruction following the instruction on which the INTR signaloccurred.Program State ChangeA program-state change does not accompany interrupts generated by the INT ninstruction or the INTR signal.
The INT n instruction generates the interrupt withinthe instruction stream. When the processor receives an INTR signal, it commits allstate changes for all previous instructions before it responds to the interrupt; so,program execution can resume upon returning from the interrupt handler.Vol. 3 5-67INTERRUPT AND EXCEPTION HANDLING5-68 Vol.
3CHAPTER 6TASK MANAGEMENTThis chapter describes the IA-32 architecture’s task management facilities. Thesefacilities are only available when the processor is running in protected mode.This chapter focuses on 32-bit tasks and the 32-bit TSS structure. For information on16-bit tasks and the 16-bit TSS structure, see Section 6.6, “16-Bit Task-StateSegment (TSS).” For information specific to task management in 64-bit mode, seeSection 6.7, “Task Management in 64-bit Mode.”6.1TASK MANAGEMENT OVERVIEWA task is a unit of work that a processor can dispatch, execute, and suspend. It canbe used to execute a program, a task or process, an operating-system service utility,an interrupt or exception handler, or a kernel or executive utility.The IA-32 architecture provides a mechanism for saving the state of a task, fordispatching tasks for execution, and for switching from one task to another.
Whenoperating in protected mode, all processor execution takes place from within a task.Even simple systems must define at least one task. More complex systems can usethe processor’s task management facilities to support multitasking applications.6.1.1Task StructureA task is made up of two parts: a task execution space and a task-state segment(TSS). The task execution space consists of a code segment, a stack segment, andone or more data segments (see Figure 6-1). If an operating system or executiveuses the processor’s privilege-level protection mechanism, the task execution spacealso provides a separate stack for each privilege level.The TSS specifies the segments that make up the task execution space and providesa storage place for task state information.
In multitasking systems, the TSS alsoprovides a mechanism for linking tasks.A task is identified by the segment selector for its TSS. When a task is loaded into theprocessor for execution, the segment selector, base address, limit, and segmentdescriptor attributes for the TSS are loaded into the task register (see Section 2.4.4,“Task Register (TR)”).If paging is implemented for the task, the base address of the page directory used bythe task is loaded into control register CR3.Vol.
3 6-1TASK MANAGEMENTCodeSegmentTask-StateSegment(TSS)DataSegmentStackSegment(Current Priv.Level)Stack Seg.Priv. Level 0Stack Seg.Priv. Level 1Task RegisterCR3StackSegment(Priv. Level 2)Figure 6-1. Structure of a Task6.1.2Task StateThe following items define the state of the currently executing task:•The task’s current execution space, defined by the segment selectors in thesegment registers (CS, DS, SS, ES, FS, and GS).•••••••••The state of the general-purpose registers.The state of the EFLAGS register.The state of the EIP register.The state of control register CR3.The state of the task register.The state of the LDTR register.The I/O map base address and I/O map (contained in the TSS).Stack pointers to the privilege 0, 1, and 2 stacks (contained in the TSS).Link to previously executed task (contained in the TSS).Prior to dispatching a task, all of these items are contained in the task’s TSS, exceptthe state of the task register.
Also, the complete contents of the LDTR register are notcontained in the TSS, only the segment selector for the LDT.6-2 Vol. 3TASK MANAGEMENT6.1.3Executing a TaskSoftware or the processor can dispatch a task for execution in one of the followingways:•••••A explicit call to a task with the CALL instruction.A explicit jump to a task with the JMP instruction.An implicit call (by the processor) to an interrupt-handler task.An implicit call to an exception-handler task.A return (initiated with an IRET instruction) when the NT flag in the EFLAGSregister is set.All of these methods for dispatching a task identify the task to be dispatched with asegment selector that points to a task gate or the TSS for the task.
When dispatchinga task with a CALL or JMP instruction, the selector in the instruction may select theTSS directly or a task gate that holds the selector for the TSS. When dispatching atask to handle an interrupt or exception, the IDT entry for the interrupt or exceptionmust contain a task gate that holds the selector for the interrupt- or exceptionhandler TSS.When a task is dispatched for execution, a task switch occurs between the currentlyrunning task and the dispatched task. During a task switch, the execution environment of the currently executing task (called the task’s state or context) is saved inits TSS and execution of the task is suspended. The context for the dispatched task isthen loaded into the processor and execution of that task begins with the instructionpointed to by the newly loaded EIP register.
If the task has not been run since thesystem was last initialized, the EIP will point to the first instruction of the task’s code;otherwise, it will point to the next instruction after the last instruction that the taskexecuted when it was last active.If the currently executing task (the calling task) called the task being dispatched (thecalled task), the TSS segment selector for the calling task is stored in the TSS of thecalled task to provide a link back to the calling task.For all IA-32 processors, tasks are not recursive.
A task cannot call or jump to itself.Interrupts and exceptions can be handled with a task switch to a handler task. Here,the processor performs a task switch to handle the interrupt or exception and automatically switches back to the interrupted task upon returning from the interrupthandler task or exception-handler task. This mechanism can also handle interruptsthat occur during interrupt tasks.As part of a task switch, the processor can also switch to another LDT, allowing eachtask to have a different logical-to-physical address mapping for LDT-based segments.The page-directory base register (CR3) also is reloaded on a task switch, allowingeach task to have its own set of page tables.
These protection facilities help isolatetasks and prevent them from interfering with one another.If protection mechanisms are not used, the processor provides no protectionbetween tasks. This is true even with operating systems that use multiple privilegelevels for protection. A task running at privilege level 3 that uses the same LDT andVol. 3 6-3TASK MANAGEMENTpage tables as other privilege-level-3 tasks can access code and corrupt data and thestack of other tasks.Use of task management facilities for handling multitasking applications is optional.Multitasking can be handled in software, with each software defined task executed inthe context of a single IA-32 architecture task.6.2TASK MANAGEMENT DATA STRUCTURESThe processor defines five data structures for handling task-related activities:•••••Task-state segment (TSS).Task-gate descriptor.TSS descriptor.Task register.NT flag in the EFLAGS register.When operating in protected mode, a TSS and TSS descriptor must be created for atleast one task, and the segment selector for the TSS must be loaded into the taskregister (using the LTR instruction).6.2.1Task-State Segment (TSS)The processor state information needed to restore a task is saved in a systemsegment called the task-state segment (TSS).
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
