Volume 3A System Programming Guide_ Part 1 (794103), страница 62
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Page-Fault Error Code•The contents of the CR2 register. The processor loads the CR2 register with the32-bit linear address that generated the exception. The page-fault handler canuse this address to locate the corresponding page directory and page-tableentries. Another page fault can potentially occur during execution of the pagefault handler; the handler should save the contents of the CR2 register before asecond page fault can occur.1 If a page fault is caused by a page-level protection1.
Processors update CR2 whenever a page fault is detected. If a second page fault occurs while anearlier page fault is being delivered, the faulting linear address of the second fault will overwritethe contents of CR2 (replacing the previous address). These updates to CR2 occur even if thepage fault results in a double fault or occurs during the delivery of a double fault.Vol. 3 5-55INTERRUPT AND EXCEPTION HANDLINGviolation, the access flag in the page-directory entry is set when the fault occurs.The behavior of IA-32 processors regarding the access flag in the correspondingpage-table entry is model specific and not architecturally defined.Saved Instruction PointerThe saved contents of CS and EIP registers generally point to the instruction thatgenerated the exception.
If the page-fault exception occurred during a task switch,the CS and EIP registers may point to the first instruction of the new task (asdescribed in the following “Program State Change” section).Program State ChangeA program-state change does not normally accompany a page-fault exception,because the instruction that causes the exception to be generated is not executed.After the page-fault exception handler has corrected the violation (for example,loaded the missing page into memory), execution of the program or task can beresumed.When a page-fault exception is generated during a task switch, the program-statemay change, as follows. During a task switch, a page-fault exception can occurduring any of following operations:••••While writing the state of the original task into the TSS of that task.•While reading the LDT of the new task to verify the segment registers stored inthe new TSS.While reading the GDT to locate the TSS descriptor of the new task.While reading the TSS of the new task.While reading segment descriptors associated with segment selectors from thenew task.In the last two cases the exception occurs in the context of the new task.
The instruction pointer refers to the first instruction of the new task, not to the instruction whichcaused the task switch (or the last instruction to be executed, in the case of an interrupt). If the design of the operating system permits page faults to occur during taskswitches, the page-fault handler should be called through a task gate.If a page fault occurs during a task switch, the processor will load all the state information from the new TSS (without performing any additional limit, present, or typechecks) before it generates the exception.
The page-fault handler should thus notrely on being able to use the segment selectors found in the CS, SS, DS, ES, FS, andGS registers without causing another exception. (See the Program State Changedescription for “Interrupt 10—Invalid TSS Exception (#TS)” in this chapter for additional information on how to handle this situation.)Additional Exception-Handling InformationSpecial care should be taken to ensure that an exception that occurs during anexplicit stack switch does not cause the processor to use an invalid stack pointer5-56 Vol. 3INTERRUPT AND EXCEPTION HANDLING(SS:ESP). Software written for 16-bit IA-32 processors often use a pair of instructions to change to a new stack, for example:MOV SS, AXMOV SP, StackTopWhen executing this code on one of the 32-bit IA-32 processors, it is possible to geta page fault, general-protection fault (#GP), or alignment check fault (#AC) after thesegment selector has been loaded into the SS register but before the ESP registerhas been loaded.
At this point, the two parts of the stack pointer (SS and ESP) areinconsistent. The new stack segment is being used with the old stack pointer.The processor does not use the inconsistent stack pointer if the exception handlerswitches to a well defined stack (that is, the handler is a task or a more privilegedprocedure). However, if the exception handler is called at the same privilege leveland from the same task, the processor will attempt to use the inconsistent stackpointer.In systems that handle page-fault, general-protection, or alignment check exceptions within the faulting task (with trap or interrupt gates), software executing at thesame privilege level as the exception handler should initialize a new stack by usingthe LSS instruction rather than a pair of MOV instructions, as described earlier in thisnote.
When the exception handler is running at privilege level 0 (the normal case),the problem is limited to procedures or tasks that run at privilege level 0, typicallythe kernel of the operating system.Vol. 3 5-57INTERRUPT AND EXCEPTION HANDLINGInterrupt 16—x87 FPU Floating-Point Error (#MF)Exception ClassFault.DescriptionIndicates that the x87 FPU has detected a floating-point error.
The NE flag in theregister CR0 must be set for an interrupt 16 (floating-point error exception) to begenerated. (See Section 2.5, “Control Registers,” for a detailed description of the NEflag.)NOTESIMD floating-point exceptions (#XF) are signaled through interrupt19.While executing x87 FPU instructions, the x87 FPU detects and reports six types offloating-point error conditions:•Invalid operation (#I)— Stack overflow or underflow (#IS)— Invalid arithmetic operation (#IA)•••••Divide-by-zero (#Z)Denormalized operand (#D)Numeric overflow (#O)Numeric underflow (#U)Inexact result (precision) (#P)Each of these error conditions represents an x87 FPU exception type, and for each ofexception type, the x87 FPU provides a flag in the x87 FPU status register and a maskbit in the x87 FPU control register.
If the x87 FPU detects a floating-point error andthe mask bit for the exception type is set, the x87 FPU handles the exception automatically by generating a predefined (default) response and continuing programexecution. The default responses have been designed to provide a reasonable resultfor most floating-point applications.If the mask for the exception is clear and the NE flag in register CR0 is set, the x87FPU does the following:1. Sets the necessary flag in the FPU status register.2.
Waits until the next “waiting” x87 FPU instruction or WAIT/FWAIT instruction isencountered in the program’s instruction stream.3. Generates an internal error signal that cause the processor to generate afloating-point exception (#MF).5-58 Vol. 3INTERRUPT AND EXCEPTION HANDLINGPrior to executing a waiting x87 FPU instruction or the WAIT/FWAIT instruction, thex87 FPU checks for pending x87 FPU floating-point exceptions (as described in step 2above). Pending x87 FPU floating-point exceptions are ignored for “non-waiting” x87FPU instructions, which include the FNINIT, FNCLEX, FNSTSW, FNSTSW AX, FNSTCW,FNSTENV, and FNSAVE instructions.
Pending x87 FPU exceptions are also ignoredwhen executing the state management instructions FXSAVE and FXRSTOR.All of the x87 FPU floating-point error conditions can be recovered from. The x87 FPUfloating-point-error exception handler can determine the error condition that causedthe exception from the settings of the flags in the x87 FPU status word.
See “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information on handling x87 FPUfloating-point exceptions.Exception Error CodeNone. The x87 FPU provides its own error information.Saved Instruction PointerThe saved contents of CS and EIP registers point to the floating-point or WAIT/FWAITinstruction that was about to be executed when the floating-point-error exceptionwas generated.
This is not the faulting instruction in which the error condition wasdetected. The address of the faulting instruction is contained in the x87 FPU instruction pointer register. See “x87 FPU Instruction and Operand (Data) Pointers” inChapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 1, for more information about information the FPU saves for use in handlingfloating-point-error exceptions.Program State ChangeA program-state change generally accompanies an x87 FPU floating-point exceptionbecause the handling of the exception is delayed until the next waiting x87 FPUfloating-point or WAIT/FWAIT instruction following the faulting instruction.
The x87FPU, however, saves sufficient information about the error condition to allowrecovery from the error and re-execution of the faulting instruction if needed.In situations where non- x87 FPU floating-point instructions depend on the results ofan x87 FPU floating-point instruction, a WAIT or FWAIT instruction can be inserted infront of a dependent instruction to force a pending x87 FPU floating-point exceptionto be handled before the dependent instruction is executed. See “x87 FPU ExceptionSynchronization” in Chapter 8 of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 1, for more information about synchronization of x87floating-point-error exceptions.Vol. 3 5-59INTERRUPT AND EXCEPTION HANDLINGInterrupt 17—Alignment Check Exception (#AC)Exception ClassFault.DescriptionIndicates that the processor detected an unaligned memory operand when alignmentchecking was enabled.
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