Volume 3A System Programming Guide_ Part 1 (794103), страница 58
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The savedcontents of CS and EIP registers point to the next instruction to be executed at thepoint the interrupt is taken. See Section 5.5, “Exception Classifications,” for moreinformation about when the processor takes NMI interrupts.Program State ChangeThe instruction executing when an NMI interrupt is received is completed before theNMI is generated.
A program or task can thus be restarted upon returning from aninterrupt handler without loss of continuity, provided the interrupt handler saves thestate of the processor before handling the interrupt and restores the processor’sstate prior to a return.5-30 Vol. 3INTERRUPT AND EXCEPTION HANDLINGInterrupt 3—Breakpoint Exception (#BP)Exception ClassTrap.DescriptionIndicates that a breakpoint instruction (INT 3) was executed, causing a breakpointtrap to be generated.
Typically, a debugger sets a breakpoint by replacing the firstopcode byte of an instruction with the opcode for the INT 3 instruction. (The INT 3instruction is one byte long, which makes it easy to replace an opcode in a codesegment in RAM with the breakpoint opcode.) The operating system or a debuggingtool can use a data segment mapped to the same physical address space as the codesegment to place an INT 3 instruction in places where it is desired to call thedebugger.With the P6 family, Pentium, Intel486, and Intel386 processors, it is more convenientto set breakpoints with the debug registers.
(See Section 18.3.2, “Breakpoint Exception (#BP)—Interrupt Vector 3,” for information about the breakpoint exception.) Ifmore breakpoints are needed beyond what the debug registers allow, the INT 3instruction can be used.The breakpoint (#BP) exception can also be generated by executing the INT ninstruction with an operand of 3. The action of this instruction (INT 3) is slightlydifferent than that of the INT 3 instruction (see “INTn/INTO/INT3—Call to InterruptProcedure” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).Exception Error CodeNone.Saved Instruction PointerSaved contents of CS and EIP registers point to the instruction following the INT 3instruction.Program State ChangeEven though the EIP points to the instruction following the breakpoint instruction, thestate of the program is essentially unchanged because the INT 3 instruction does notaffect any register or memory locations.
The debugger can thus resume thesuspended program by replacing the INT 3 instruction that caused the breakpointwith the original opcode and decrementing the saved contents of the EIP register.Upon returning from the debugger, program execution resumes with the replacedinstruction.Vol. 3 5-31INTERRUPT AND EXCEPTION HANDLINGInterrupt 4—Overflow Exception (#OF)Exception ClassTrap.DescriptionIndicates that an overflow trap occurred when an INTO instruction was executed. TheINTO instruction checks the state of the OF flag in the EFLAGS register.
If the OF flagis set, an overflow trap is generated.Some arithmetic instructions (such as the ADD and SUB) perform both signed andunsigned arithmetic. These instructions set the OF and CF flags in the EFLAGSregister to indicate signed overflow and unsigned overflow, respectively. Whenperforming arithmetic on signed operands, the OF flag can be tested directly or theINTO instruction can be used. The benefit of using the INTO instruction is that if theoverflow exception is detected, an exception handler can be called automatically tohandle the overflow condition.Exception Error CodeNone.Saved Instruction PointerThe saved contents of CS and EIP registers point to the instruction following the INTOinstruction.Program State ChangeEven though the EIP points to the instruction following the INTO instruction, the stateof the program is essentially unchanged because the INTO instruction does not affectany register or memory locations.
The program can thus resume normal executionupon returning from the overflow exception handler.5-32 Vol. 3INTERRUPT AND EXCEPTION HANDLINGInterrupt 5—BOUND Range Exceeded Exception (#BR)Exception ClassFault.DescriptionIndicates that a BOUND-range-exceeded fault occurred when a BOUND instructionwas executed. The BOUND instruction checks that a signed array index is within theupper and lower bounds of an array located in memory.
If the array index is notwithin the bounds of the array, a BOUND-range-exceeded fault is generated.Exception Error CodeNone.Saved Instruction PointerThe saved contents of CS and EIP registers point to the BOUND instruction thatgenerated the exception.Program State ChangeA program-state change does not accompany the bounds-check fault, because theoperands for the BOUND instruction are not modified.
Returning from the BOUNDrange-exceeded exception handler causes the BOUND instruction to be restarted.Vol. 3 5-33INTERRUPT AND EXCEPTION HANDLINGInterrupt 6—Invalid Opcode Exception (#UD)Exception ClassFault.DescriptionIndicates that the processor did one of the following things:••Attempted to execute an invalid or reserved opcode.•Attempted to execute an MMX or SSE/SSE2/SSE3 instruction on an Intel 64 orIA-32 processor that does not support the MMX technology orSSE/SSE2/SSE3/SSSE3 extensions, respectively. CPUID feature flags MMX (bit23), SSE (bit 25), SSE2 (bit 26), SSE3 (ECX, bit 0), SSSE3 (ECX, bit 9) indicatesupport for these extensions.•Attempted to execute an MMX instruction or SSE/SSE2/SSE3/SSSE3 SIMDinstruction (with the exception of the MOVNTI, PAUSE, PREFETCHh, SFENCE,LFENCE, MFENCE, CLFLUSH, MONITOR, and MWAIT instructions) when the EMflag in control register CR0 is set (1).•Attempted to execute an SSE/SE2/SSE3/SSSE3 instruction when the OSFXSR bitin control register CR4 is clear (0).
Note this does not include the followingSSE/SSE2/SSE3 instructions: MASKMOVQ, MOVNTQ, MOVNTI, PREFETCHh,SFENCE, LFENCE, MFENCE, and CLFLUSH; or the 64-bit versions of the PAVGB,PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB,PMULHUW, PSADBW, PSHUFW, PADDQ, PSUBQ, PALIGNR, PABSB, PABSD,PABSW, PHADDD, PHADDSW, PHADDW, PHSUBD, PHSUBSW, PHSUBW,PMADDUBSM, PMULHRSW, PSHUFB, PSIGNB, PSIGND, and PSIGNW.•Attempted to execute an SSE/SSE2/SSE3/SSSE3 instruction on an Intel 64 orIA-32 processor that caused a SIMD floating-point exception when theOSXMMEXCPT bit in control register CR4 is clear (0).•Executed a UD2 instruction. Note that even though it is the execution of the UD2instruction that causes the invalid opcode exception, the saved instructionpointer will still points at the UD2 instruction.•Detected a LOCK prefix that precedes an instruction that may not be locked orone that may be locked but the destination operand is not a memory location.•Attempted to execute an LLDT, SLDT, LTR, STR, LSL, LAR, VERR, VERW, or ARPLinstruction while in real-address or virtual-8086 mode.•Attempted to execute the RSM instruction when not in SMM mode.Attempted to execute an instruction with an operand type that is invalid for itsaccompanying opcode; for example, the source operand for a LES instruction isnot a memory location.In Intel 64 and IA-32 processors that implement out-of-order execution microarchitectures, this exception is not generated until an attempt is made to retire the resultof executing an invalid instruction; that is, decoding and speculatively attempting toexecute an invalid opcode does not generate this exception.
Likewise, in the Pentium5-34 Vol. 3INTERRUPT AND EXCEPTION HANDLINGprocessor and earlier IA-32 processors, this exception is not generated as the resultof prefetching and preliminary decoding of an invalid instruction. (See Section 5.5,“Exception Classifications,” for general rules for taking of interrupts and exceptions.)The opcodes D6 and F1 are undefined opcodes reserved by the Intel 64 and IA-32architectures. These opcodes, even though undefined, do not generate an invalidopcode exception.The UD2 instruction is guaranteed to generate an invalid opcode exception.Exception Error CodeNone.Saved Instruction PointerThe saved contents of CS and EIP registers point to the instruction that generated theexception.Program State ChangeA program-state change does not accompany an invalid-opcode fault, because theinvalid instruction is not executed.Vol. 3 5-35INTERRUPT AND EXCEPTION HANDLINGInterrupt 7—Device Not Available Exception (#NM)Exception ClassFault.DescriptionIndicates one of the following things:The device-not-available exception is generated by either of three conditions:•The processor executed an x87 FPU floating-point instruction while the EM flag incontrol register CR0 was set (1).
See the paragraph below for the special case ofthe WAIT/FWAIT instruction.•The processor executed a WAIT/FWAIT instruction while the MP and TS flags ofregister CR0 were set, regardless of the setting of the EM flag.•The processor executed an x87 FPU, MMX, or SSE/SSE2/SSE3 instruction (withthe exception of MOVNTI, PAUSE, PREFETCHh, SFENCE, LFENCE, MFENCE, andCLFLUSH) while the TS flag in control register CR0 was set and the EM flag isclear.The EM flag is set when the processor does not have an internal x87 FPU floatingpoint unit. A device-not-available exception is then generated each time an x87 FPUfloating-point instruction is encountered, allowing an exception handler to callfloating-point instruction emulation routines.The TS flag indicates that a context switch (task switch) has occurred since the lasttime an x87 floating-point, MMX, or SSE/SSE2/SSE3 instruction was executed; butthat the context of the x87 FPU, XMM, and MXCSR registers were not saved.
Whenthe TS flag is set and the EM flag is clear, the processor generates a device-not-available exception each time an x87 floating-point, MMX, or SSE/SSE2/SSE3 instructionis encountered (with the exception of the instructions listed above). The exceptionhandler can then save the context of the x87 FPU, XMM, and MXCSR registers beforeit executes the instruction. See Section 2.5, “Control Registers,” for more informationabout the TS flag.The MP flag in control register CR0 is used along with the TS flag to determine if WAITor FWAIT instructions should generate a device-not-available exception. It extendsthe function of the TS flag to the WAIT and FWAIT instructions, giving the exceptionhandler an opportunity to save the context of the x87 FPU before the WAIT or FWAITinstruction is executed. The MP flag is provided primarily for use with the Intel 286and Intel386 DX processors. For programs running on the Pentium 4, Intel Xeon, P6family, Pentium, or Intel486 DX processors, or the Intel 487 SX coprocessors, the MPflag should always be set; for programs running on the Intel486 SX processor, the MPflag should be clear.Exception Error CodeNone.5-36 Vol.
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