Volume 3A System Programming Guide_ Part 1 (794103), страница 56
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3 5-19INTERRUPT AND EXCEPTION HANDLINGof the EFLAGS register on the stack. Accessing a handler procedure through a trapgate does not affect the IF flag.5.12.2Interrupt TasksWhen an exception or interrupt handler is accessed through a task gate in the IDT, atask switch results. Handling an exception or interrupt with a separate task offersseveral advantages:••The entire context of the interrupted program or task is saved automatically.•The handler can be further isolated from other tasks by giving it a separateaddress space.
This is done by giving it a separate LDT.A new TSS permits the handler to use a new privilege level 0 stack when handlingthe exception or interrupt. If an exception or interrupt occurs when the currentprivilege level 0 stack is corrupted, accessing the handler through a task gate canprevent a system crash by providing the handler with a new privilege level 0stack.The disadvantage of handling an interrupt with a separate task is that the amount ofmachine state that must be saved on a task switch makes it slower than using aninterrupt gate, resulting in increased interrupt latency.A task gate in the IDT references a TSS descriptor in the GDT (see Figure 5-5). Aswitch to the handler task is handled in the same manner as an ordinary task switch(see Section 6.3, “Task Switching”).
The link back to the interrupted task is stored inthe previous task link field of the handler task’s TSS. If an exception caused an errorcode to be generated, this error code is copied to the stack of the new task.When exception- or interrupt-handler tasks are used in an operating system, thereare actually two mechanisms that can be used to dispatch tasks: the software scheduler (part of the operating system) and the hardware scheduler (part of theprocessor's interrupt mechanism).
The software scheduler needs to accommodateinterrupt tasks that may be dispatched when interrupts are enabled.NOTEBecause IA-32 architecture tasks are not re-entrant, an interrupthandler task must disable interrupts between the time it completeshandling the interrupt and the time it executes the IRET instruction.This action prevents another interrupt from occurring while theinterrupt task’s TSS is still marked busy, which would cause ageneral-protection (#GP) exception.5-20 Vol. 3INTERRUPT AND EXCEPTION HANDLINGIDTInterruptVectorTSS for InterruptHandling TaskTask GateTSS SelectorGDTTSSBaseAddressTSS DescriptorFigure 5-5.
Interrupt Task Switch5.13ERROR CODEWhen an exception condition is related to a specific segment, the processor pushesan error code onto the stack of the exception handler (whether it is a procedure ortask). The error code has the format shown in Figure 5-6. The error code resemblesa segment selector; however, instead of a TI flag and RPL field, the error codecontains 3 flags:EXTExternal event (bit 0) — When set, indicates that an event externalto the program, such as a hardware interrupt, caused the exception.IDTDescriptor location (bit 1) — When set, indicates that the indexportion of the error code refers to a gate descriptor in the IDT; whenVol.
3 5-21INTERRUPT AND EXCEPTION HANDLINGclear, indicates that the index refers to a descriptor in the GDT or thecurrent LDT.TIGDT/LDT (bit 2) — Only used when the IDT flag is clear. When set,the TI flag indicates that the index portion of the error code refers toa segment or gate descriptor in the LDT; when clear, it indicates thatthe index refers to a descriptor in the current GDT.313 2 1 0ReservedSegment Selector IndexT I EXI DT TFigure 5-6. Error CodeThe segment selector index field provides an index into the IDT, GDT, or current LDTto the segment or gate selector being referenced by the error code. In some casesthe error code is null (that is, all bits in the lower word are clear).
A null error codeindicates that the error was not caused by a reference to a specific segment or that anull segment descriptor was referenced in an operation.The format of the error code is different for page-fault exceptions (#PF).
See the“Interrupt 14—Page-Fault Exception (#PF)” section in this chapter.The error code is pushed on the stack as a doubleword or word (depending on thedefault interrupt, trap, or task gate size). To keep the stack aligned for doublewordpushes, the upper half of the error code is reserved. Note that the error code is notpopped when the IRET instruction is executed to return from an exception handler, sothe handler must remove the error code before executing a return.Error codes are not pushed on the stack for exceptions that are generated externally(with the INTR or LINT[1:0] pins) or the INT n instruction, even if an error code isnormally produced for those exceptions.5.14EXCEPTION AND INTERRUPT HANDLING IN 64-BITMODEIn 64-bit mode, interrupt and exception handling is similar to what has beendescribed for non-64-bit modes.
The following are the exceptions:•All interrupt handlers pointed by the IDT are in 64-bit code (this does not apply tothe SMI handler).•The size of interrupt-stack pushes is fixed at 64 bits; and the processor uses8-byte, zero extended stores.5-22 Vol. 3INTERRUPT AND EXCEPTION HANDLING•The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacymodes, this push is conditional and based on a change in current privilege level(CPL).••••The new SS is set to NULL if there is a change in CPL.IRET behavior changes.There is a new interrupt stack-switch mechanism.The alignment of interrupt stack frame is different.5.14.164-Bit Mode IDTInterrupt and trap gates are 16 bytes in length to provide a 64-bit offset for theinstruction pointer (RIP).
The 64-bit RIP referenced by interrupt-gate descriptorsallows an interrupt service routine to be located anywhere in the linear-addressspace. See Figure 5-7.Interrupt/Trap Gate310Reserved12310Offset 63..3231816 15 14 13 12 11Offset 31..16PDP08 7TYPE5 420 0 0 0 004ISTL3116 15Segment SelectorDPLOffsetPSelectorIST0Offset 15..00Descriptor Privilege LevelOffset to procedure entry pointSegment Present flagSegment Selector for destination code segmentInterrupt Stack TableFigure 5-7.
64-Bit IDT Gate DescriptorsIn 64-bit mode, the IDT index is formed by scaling the interrupt vector by 16. Thefirst eight bytes (bytes 7:0) of a 64-bit mode interrupt gate are similar but not identical to legacy 32-bit interrupt gates. The type field (bits 11:8 in bytes 7:4) isdescribed in Table 3-2. The Interrupt Stack Table (IST) field (bits 4:0 in bytes 7:4) isused by the stack switching mechanisms described in Section 5.14.5, “InterruptStack Table.” Bytes 11:8 hold the upper 32 bits of the target RIP (interrupt segmentoffset) in canonical form.
A general-protection exception (#GP) is generated if soft-Vol. 3 5-23INTERRUPT AND EXCEPTION HANDLINGware attempts to reference an interrupt gate with a target RIP that is not in canonicalform.The target code segment referenced by the interrupt gate must be a 64-bit codesegment (CS.L = 1, CS.D = 0). If the target is not a 64-bit code segment, a generalprotection exception (#GP) is generated with the IDT vector number reported as theerror code.Only 64-bit interrupt and trap gates can be referenced in IA-32e mode (64-bit modeand compatibility mode).
Legacy 32-bit interrupt or trap gate types (0EH or 0FH) areredefined in IA-32e mode as 64-bit interrupt and trap gate types. No 32-bit interruptor trap gate type exists in IA-32e mode. If a reference is made to a 16-bit interruptor trap gate (06H or 07H), a general-protection exception (#GP(0)) is generated.5.14.264-Bit Mode Stack FrameIn legacy mode, the size of an IDT entry (16 bits or 32 bits) determines the size ofinterrupt-stack-frame pushes. SS:ESP is pushed only on a CPL change. In 64-bitmode, the size of interrupt stack-frame pushes is fixed at eight bytes.
This is becauseonly 64-bit mode gates can be referenced. 64-bit mode also pushes SS:RSP unconditionally, rather than only on a CPL change.Aside from error codes, pushing SS:RSP unconditionally presents operating systemswith a consistent interrupt-stackframe size across all interrupts. Interrupt serviceroutine entry points that handle interrupts generated by the INTn instruction orexternal INTR# signal can push an additional error code place-holder to maintainconsistency.In legacy mode, the stack pointer may be at any alignment when an interrupt orexception causes a stack frame to be pushed.
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