Volume 3A System Programming Guide_ Part 1 (794103), страница 55
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This register holds both a32-bit base address and 16-bit limit for the IDT.The LIDT (load IDT register) and SIDT (store IDT register) instructions load and storethe contents of the IDTR register, respectively. The LIDT instruction loads the IDTRregister with the base address and limit held in a memory operand. This instructioncan be executed only when the CPL is 0. It normally is used by the initialization codeof an operating system when creating an IDT.
An operating system also may use it tochange from one IDT to another. The SIDT instruction copies the base and limit valuestored in IDTR to memory. This instruction can be executed at any privilege level.If a vector references a descriptor beyond the limit of the IDT, a general-protectionexception (#GP) is generated.NOTEBecause interrupts are delivered to the processor core only once, anincorrectly configured IDT could result in incomplete interrupthandling and/or the blocking of interrupt delivery.IA-32 architecture rules need to be followed for setting up IDTRbase/limit/access fields and each field in the gate descriptors. Thesame apply for the Intel 64 architecture. This includes implicitreferencing of the destination code segment through the GDT or LDTand accessing the stack.Vol. 3 5-13INTERRUPT AND EXCEPTION HANDLINGIDTR Register4716 15IDT Base Address0IDT Limit+InterruptDescriptor Table (IDT)Gate forInterrupt #n(n−1)∗8Gate forInterrupt #316Gate forInterrupt #28Gate forInterrupt #13100Figure 5-1.
Relationship of the IDTR and IDT5.11IDT DESCRIPTORSThe IDT may contain any of three kinds of gate descriptors:•••Task-gate descriptorInterrupt-gate descriptorTrap-gate descriptorFigure 5-2 shows the formats for the task-gate, interrupt-gate, and trap-gatedescriptors. The format of a task gate used in an IDT is the same as that of a taskgate used in the GDT or an LDT (see Section 6.2.5, “Task-Gate Descriptor”). The taskgate contains the segment selector for a TSS for an exception and/or interrupthandler task.Interrupt and trap gates are very similar to call gates (see Section 4.8.3, “CallGates”).
They contain a far pointer (segment selector and offset) that the processoruses to transfer program execution to a handler procedure in an exception- or interrupt-handler code segment. These gates differ in the way the processor handles theIF flag in the EFLAGS register (see Section 5.12.1.2, “Flag Usage By Exception- orInterrupt-Handler Procedure”).5-14 Vol. 3INTERRUPT AND EXCEPTION HANDLINGTask Gate3116 15 14 13 12P31DPL08 740 0 1 0 116 150TSS Segment Selector0Interrupt Gate3116 15 14 13 12Offset 31..1631PDPL8 70 D 1 1 05 400 0 016 1540Segment SelectorOffset 15..00Trap Gate3116 15 14 13 12Offset 31..1631PDPL8 70 D 1 1 15 40 0 016 15Segment SelectorDPLOffsetPSelectorD040Offset 15..00Descriptor Privilege LevelOffset to procedure entry pointSegment Present flagSegment Selector for destination code segmentSize of gate: 1 = 32 bits; 0 = 16 bitsReservedFigure 5-2.
IDT Gate Descriptors5.12EXCEPTION AND INTERRUPT HANDLINGThe processor handles calls to exception- and interrupt-handlers similar to the way ithandles calls with a CALL instruction to a procedure or a task. When responding to anexception or interrupt, the processor uses the exception or interrupt vector as anindex to a descriptor in the IDT. If the index points to an interrupt gate or trap gate,the processor calls the exception or interrupt handler in a manner similar to a CALLto a call gate (see Section 4.8.2, “Gate Descriptors,” through Section 4.8.6,Vol. 3 5-15INTERRUPT AND EXCEPTION HANDLING“Returning from a Called Procedure”).
If index points to a task gate, the processorexecutes a task switch to the exception- or interrupt-handler task in a manner similarto a CALL to a task gate (see Section 6.3, “Task Switching”).5.12.1Exception- or Interrupt-Handler ProceduresAn interrupt gate or trap gate references an exception- or interrupt-handler procedure that runs in the context of the currently executing task (see Figure 5-3). Thesegment selector for the gate points to a segment descriptor for an executable codesegment in either the GDT or the current LDT. The offset field of the gate descriptorpoints to the beginning of the exception- or interrupt-handling procedure.DestinationCode SegmentIDTOffsetInterruptVectorInterrupt orTrap Gate+Segment SelectorGDT or LDTBaseAddressSegmentDescriptorFigure 5-3.
Interrupt Procedure Call5-16 Vol. 3InterruptProcedureINTERRUPT AND EXCEPTION HANDLINGWhen the processor performs a call to the exception- or interrupt-handler procedure:•If the handler procedure is going to be executed at a numerically lower privilegelevel, a stack switch occurs. When the stack switch occurs:a. The segment selector and stack pointer for the stack to be used by thehandler are obtained from the TSS for the currently executing task.
On thisnew stack, the processor pushes the stack segment selector and stackpointer of the interrupted procedure.b. The processor then saves the current state of the EFLAGS, CS, and EIPregisters on the new stack (see Figures 5-4).c.•If an exception causes an error code to be saved, it is pushed on the newstack after the EIP value.If the handler procedure is going to be executed at the same privilege level as theinterrupted procedure:a.
The processor saves the current state of the EFLAGS, CS, and EIP registerson the current stack (see Figures 5-4).b. If an exception causes an error code to be saved, it is pushed on the currentstack after the EIP value.Vol. 3 5-17INTERRUPT AND EXCEPTION HANDLINGStack Usage with NoPrivilege-Level ChangeInterrupted Procedure’sand Handler’s StackEFLAGSCSEIPError CodeESP BeforeTransfer to HandlerESP AfterTransfer to HandlerStack Usage withPrivilege-Level ChangeInterrupted Procedure’sStackHandler’s StackESP BeforeTransfer to HandlerESP AfterTransfer to HandlerSSESPEFLAGSCSEIPError CodeFigure 5-4. Stack Usage on Transfers to Interrupt and Exception-Handling RoutinesTo return from an exception- or interrupt-handler procedure, the handler must usethe IRET (or IRETD) instruction.
The IRET instruction is similar to the RET instructionexcept that it restores the saved flags into the EFLAGS register. The IOPL field of theEFLAGS register is restored only if the CPL is 0. The IF flag is changed only if the CPLis less than or equal to the IOPL. See Chapter 3, “Instruction Set Reference, A-M,” ofthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, fora description of the complete operation performed by the IRET instruction.If a stack switch occurred when calling the handler procedure, the IRET instructionswitches back to the interrupted procedure’s stack on the return.5.12.1.1Protection of Exception- and Interrupt-Handler ProceduresThe privilege-level protection for exception- and interrupt-handler procedures issimilar to that used for ordinary procedure calls when called through a call gate (seeSection 4.8.4, “Accessing a Code Segment Through a Call Gate”).
The processor does5-18 Vol. 3INTERRUPT AND EXCEPTION HANDLINGnot permit transfer of execution to an exception- or interrupt-handler procedure in aless privileged code segment (numerically greater privilege level) than the CPL.An attempt to violate this rule results in a general-protection exception (#GP). Theprotection mechanism for exception- and interrupt-handler procedures is different inthe following ways:•Because interrupt and exception vectors have no RPL, the RPL is not checked onimplicit calls to exception and interrupt handlers.•The processor checks the DPL of the interrupt or trap gate only if an exception orinterrupt is generated with an INT n, INT 3, or INTO instruction.
Here, the CPLmust be less than or equal to the DPL of the gate. This restriction preventsapplication programs or procedures running at privilege level 3 from using asoftware interrupt to access critical exception handlers, such as the page-faulthandler, providing that those handlers are placed in more privileged codesegments (numerically lower privilege level). For hardware-generated interruptsand processor-detected exceptions, the processor ignores the DPL of interruptand trap gates.Because exceptions and interrupts generally do not occur at predictable times, theseprivilege rules effectively impose restrictions on the privilege levels at which exception and interrupt- handling procedures can run.
Either of the following techniquescan be used to avoid privilege-level violations.•The exception or interrupt handler can be placed in a conforming code segment.This technique can be used for handlers that only need to access data availableon the stack (for example, divide error exceptions). If the handler needs datafrom a data segment, the data segment needs to be accessible from privilegelevel 3, which would make it unprotected.•The handler can be placed in a nonconforming code segment with privilege level0. This handler would always run, regardless of the CPL that the interruptedprogram or task is running at.5.12.1.2Flag Usage By Exception- or Interrupt-Handler ProcedureWhen accessing an exception or interrupt handler through either an interrupt gate ora trap gate, the processor clears the TF flag in the EFLAGS register after it saves thecontents of the EFLAGS register on the stack.
(On calls to exception and interrupthandlers, the processor also clears the VM, RF, and NT flags in the EFLAGS register,after they are saved on the stack.) Clearing the TF flag prevents instruction tracingfrom affecting interrupt response. A subsequent IRET instruction restores the TF(and VM, RF, and NT) flags to the values in the saved contents of the EFLAGS registeron the stack.The only difference between an interrupt gate and a trap gate is the way theprocessor handles the IF flag in the EFLAGS register. When accessing an exceptionor interrupt-handling procedure through an interrupt gate, the processor clears theIF flag to prevent other interrupts from interfering with the current interrupt handler.A subsequent IRET instruction restores the IF flag to its value in the saved contentsVol.
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