Volume 3A System Programming Guide_ Part 1 (794103), страница 53

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Do notuse.)16#MFx87 FPU Floating-PointError (Math Fault)FaultNo17#ACAlignment CheckFaultYesAny data reference in(Zero) memory.3Nox87 FPU floating-point orWAIT/FWAIT instruction.Vol. 3 5-3INTERRUPT AND EXCEPTION HANDLINGTable 5-1. Protected-Mode Exceptions and Interrupts (Contd.)18#MCMachine CheckAbortNoError codes (if any) and sourceare model dependent.419#XFSIMD Floating-PointExceptionFaultNoSSE/SSE2/SSE3 floating-pointinstructions520-31—Intel reserved.

Do not use.32255—User Defined (Nonreserved) InterruptsInterruptExternal interrupt or INT ninstruction.NOTES:1. The UD2 instruction was introduced in the Pentium Pro processor.2. Processors after the Intel386 processor do not generate this exception.3. This exception was introduced in the Intel486 processor.4. This exception was introduced in the Pentium processor and enhanced in the P6 family processors.5. This exception was introduced in the Pentium III processor.The processor’s local APIC is normally connected to a system-based I/O APIC.

Here,external interrupts received at the I/O APIC’s pins can be directed to the local APICthrough the system bus (Pentium 4 and Intel Xeon processors) or the APIC serial bus(P6 family and Pentium processors). The I/O APIC determines the vector number ofthe interrupt and sends this number to the local APIC. When a system containsmultiple processors, processors can also send interrupts to one another by means ofthe system bus (Pentium 4 and Intel Xeon processors) or the APIC serial bus (P6family and Pentium processors).The LINT[1:0] pins are not available on the Intel486 processor and earlier Pentiumprocessors that do not contain an on-chip local APIC. These processors have dedicated NMI and INTR pins.

With these processors, external interrupts are typicallygenerated by a system-based interrupt controller (8259A), with the interrupts beingsignaled through the INTR pin.Note that several other pins on the processor can cause a processor interrupt tooccur. However, these interrupts are not handled by the interrupt and exceptionmechanism described in this chapter.

These pins include the RESET#, FLUSH#,STPCLK#, SMI#, R/S#, and INIT# pins. Whether they are included on a particularprocessor is implementation dependent. Pin functions are described in the databooks for the individual processors. The SMI# pin is described in Chapter 24,“System Management.”5.3.2Maskable Hardware InterruptsAny external interrupt that is delivered to the processor by means of the INTR pin orthrough the local APIC is called a maskable hardware interrupt. Maskable hardwareinterrupts that can be delivered through the INTR pin include all IA-32 architecture5-4 Vol.

3INTERRUPT AND EXCEPTION HANDLINGdefined interrupt vectors from 0 through 255; those that can be delivered throughthe local APIC include interrupt vectors 16 through 255.The IF flag in the EFLAGS register permits all maskable hardware interrupts to bemasked as a group (see Section 5.8.1, “Masking Maskable Hardware Interrupts”).Note that when interrupts 0 through 15 are delivered through the local APIC, theAPIC indicates the receipt of an illegal vector.5.3.3Software-Generated InterruptsThe INT n instruction permits interrupts to be generated from within software bysupplying an interrupt vector number as an operand.

For example, the INT 35instruction forces an implicit call to the interrupt handler for interrupt 35.Any of the interrupt vectors from 0 to 255 can be used as a parameter in this instruction. If the processor’s predefined NMI vector is used, however, the response of theprocessor will not be the same as it would be from an NMI interrupt generated in thenormal manner. If vector number 2 (the NMI vector) is used in this instruction, theNMI interrupt handler is called, but the processor’s NMI-handling hardware is notactivated.Interrupts generated in software with the INT n instruction cannot be masked by theIF flag in the EFLAGS register.5.4SOURCES OF EXCEPTIONSThe processor receives exceptions from three sources:•••Processor-detected program-error exceptions.Software-generated exceptions.Machine-check exceptions.5.4.1Program-Error ExceptionsThe processor generates one or more exceptions when it detects program errorsduring the execution in an application program or the operating system or executive.Intel 64 and IA-32 architectures define a vector number for each processor-detectable exception.

Exceptions are classified as faults, traps, and aborts (see Section5.5, “Exception Classifications”).Vol. 3 5-5INTERRUPT AND EXCEPTION HANDLING5.4.2Software-Generated ExceptionsThe INTO, INT 3, and BOUND instructions permit exceptions to be generated in software. These instructions allow checks for exception conditions to be performed atpoints in the instruction stream. For example, INT 3 causes a breakpoint exception tobe generated.The INT n instruction can be used to emulate exceptions in software; but there is alimitation. If INT n provides a vector for one of the architecturally-defined exceptions, the processor generates an interrupt to the correct vector (to access theexception handler) but does not push an error code on the stack.

This is true even ifthe associated hardware-generated exception normally produces an error code. Theexception handler will still attempt to pop an error code from the stack while handlingthe exception. Because no error code was pushed, the handler will pop off anddiscard the EIP instead (in place of the missing error code). This sends the return tothe wrong location.5.4.3Machine-Check ExceptionsThe P6 family and Pentium processors provide both internal and external machinecheck mechanisms for checking the operation of the internal chip hardware and bustransactions.

These implementation dependent. When a machine-check error isdetected, the processor signals a machine-check exception (vector 18) and returnsan error code.See Chapter 5, “Interrupt 18—Machine-Check Exception (#MC)” and Chapter 14,“Machine-Check Architecture,” for more information about the machine-checkmechanism.5.5EXCEPTION CLASSIFICATIONSExceptions are classified as faults, traps, or aborts depending on the way they arereported and whether the instruction that caused the exception can be restartedwithout loss of program or task continuity.•Faults — A fault is an exception that can generally be corrected and that, oncecorrected, allows the program to be restarted with no loss of continuity.

When afault is reported, the processor restores the machine state to the state prior tothe beginning of execution of the faulting instruction. The return address (savedcontents of the CS and EIP registers) for the fault handler points to the faultinginstruction, rather than to the instruction following the faulting instruction.•Traps — A trap is an exception that is reported immediately following theexecution of the trapping instruction.

Traps allow execution of a program or taskto be continued without loss of program continuity. The return address for thetrap handler points to the instruction to be executed after the trappinginstruction.5-6 Vol. 3INTERRUPT AND EXCEPTION HANDLING•Aborts — An abort is an exception that does not always report the preciselocation of the instruction causing the exception and does not allow a restart ofthe program or task that caused the exception. Aborts are used to report severeerrors, such as hardware errors and inconsistent or illegal values in systemtables.NOTEOne exception subset normally reported as a fault is not restartable.Such exceptions result in loss of some processor state.

For example,executing a POPAD instruction where the stack frame crosses overthe end of the stack segment causes a fault to be reported. In thissituation, the exception handler sees that the instruction pointer(CS:EIP) has been restored as if the POPAD instruction had not beenexecuted. However, internal processor state (the general-purposeregisters) will have been modified. Such cases are consideredprogramming errors. An application causing this class of exceptionsshould be terminated by the operating system.5.6PROGRAM OR TASK RESTARTTo allow the restarting of program or task following the handling of an exception oran interrupt, all exceptions (except aborts) are guaranteed to report exceptions onan instruction boundary. All interrupts are guaranteed to be taken on an instructionboundary.For fault-class exceptions, the return instruction pointer (saved when the processorgenerates an exception) points to the faulting instruction.

So, when a program or taskis restarted following the handling of a fault, the faulting instruction is restarted (reexecuted). Restarting the faulting instruction is commonly used to handle exceptionsthat are generated when access to an operand is blocked.

The most common exampleof this type of fault is a page-fault exception (#PF) that occurs when a program ortask references an operand located on a page that is not in memory. When a pagefault exception occurs, the exception handler can load the page into memory andresume execution of the program or task by restarting the faulting instruction.

Toinsure that the restart is handled transparently to the currently executing program ortask, the processor saves the necessary registers and stack pointers to allow a restartto the state prior to the execution of the faulting instruction.For trap-class exceptions, the return instruction pointer points to the instructionfollowing the trapping instruction. If a trap is detected during an instruction whichtransfers execution, the return instruction pointer reflects the transfer. For example,if a trap is detected while executing a JMP instruction, the return instruction pointerpoints to the destination of the JMP instruction, not to the next address past the JMPinstruction. All trap exceptions allow program or task restart with no loss of continuity. For example, the overflow exception is a trap exception.

Here, the returninstruction pointer points to the instruction following the INTO instruction that testedVol. 3 5-7INTERRUPT AND EXCEPTION HANDLINGEFLAGS.OF (overflow) flag. The trap handler for this exception resolves the overflowcondition. Upon return from the trap handler, program or task execution continues atthe instruction following the INTO instruction.The abort-class exceptions do not support reliable restarting of the program or task.Abort handlers are designed to collect diagnostic information about the state of theprocessor when the abort exception occurred and then shut down the application andsystem as gracefully as possible.Interrupts rigorously support restarting of interrupted programs and tasks withoutloss of continuity. The return instruction pointer saved for an interrupt points to thenext instruction to be executed at the instruction boundary where the processor tookthe interrupt. If the instruction just executed has a repeat prefix, the interrupt istaken at the end of the current iteration with the registers set to execute the nextiteration.The ability of a P6 family processor to speculatively execute instructions does notaffect the taking of interrupts by the processor.

Interrupts are taken at instructionboundaries located during the retirement phase of instruction execution; so they arealways taken in the “in-order” instruction stream. See Chapter 2, “Intel® 64 and IA32 Architectures,” in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1, for more information about the P6 family processors’ microarchitecture and its support for out-of-order instruction execution.Note that the Pentium processor and earlier IA-32 processors also perform varyingamounts of prefetching and preliminary decoding.

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