Volume 3A System Programming Guide_ Part 1 (794103), страница 52
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Table 4-9 and Tableshow the following paging modes:•Non-PAE 4-KByte paging: 4-KByte-page only paging (CR4.PAE = 0,CR4.PSE = 0).••PSE36: 4-KByte and 4-MByte pages (CR4.PAE = 0, CR4.PSE = 1).PAE: 4-KByte and 2-MByte pages (CR4.PAE = 1, CR4.PSE = X).In legacy PAE-enabled paging, some processors may only support a 36-bit (or32-bit) physical address size; in such cases reserved bit checking still applies to bits39:36 (or bits 39:32). See the table note.Vol. 3 4-45PROTECTIONTable 4-9. IA-32e Mode Page Level Protection Matrix with Execute-Disable BitCapability EnabledModePaging ModeCheck Bits32-bit4-KByte paging (non-PAE)No reserved bits checkedPSE36 - PDE, 4-MByte pageBit [21]PSE36 - PDE, 4-KByte pageNo reserved bits checkedPSE36 - PTENo reserved bits checkedPAE - PDP table entryBits [63:40] & [8:5] & [2:1] *PAE - PDE, 2-MByte pageBits [62:40] & [20:13] *PAE - PDE, 4-KByte pageBits [62:40] *PAE - PTEBits [62:40] *PML4EBits [51:40]64-bitPDPTEBits [51:40]PDE, 2-MByte pageBits [51:40] & [20:13]PDE, 4-KByte pageBits [51:40]PTEBits [51:40]NOTES:* Reserved bit checking also applies to bits 39:36 for processors that support only 36-bits ofphysical address.
For processor that support only 32 bits of physical address, reserved bit checking also applies to bits 39:32.If execute disable bit capability is not enabled or not available, reserved bit checkingin 64-bit mode includes bit 63 and additional bits. This and reserved bit checking forlegacy 32-bit paging modes are shown in Table 4-10.4-46 Vol. 3PROTECTIONTable 4-10. Reserved Bit Checking WIth Execute-Disable Bit Capability Not EnabledModePaging ModeCheck Bits32-bitKByte paging (non-PAE)No reserved bits checked64-bitPSE36 - PDE, 4-MByte pageBit [21]PSE36 - PDE, 4-KByte pageNo reserved bits checkedPSE36 - PTENo reserved bits checkedPAE - PDP table entryBits [63:40] & [8:5] & [2:1]*PAE - PDE, 2-MByte pageBits [63:40] & [20:13]*PAE - PDE, 4-KByte pageBits [63:40]*PAE - PTEBits [63:40]*PML4EBit [63], bits [51:40]PDPTEBit [63], bits [51:40]PDE, 2-MByte pageBit [63], bits [51:40] & [20:13]PDE, 4-KByte pageBit [63], bits [51:40]PTEBit [63], bits [51:40]NOTES:* Reserved bit checking also applies to bits 39:36 for processors that support only 36-bits of physical address.
For processor that support only 32 bits of physical address, reserved bit checkingalso applies to bits 39:32.4.13.4Exception HandlingWhen execute disable bit capability is enabled (IA32_EFER.NXE = 1), conditions fora page fault to occur include the same conditions that apply to an Intel 64 or IA-32processor without execute disable bit capability plus the following new condition: aninstruction fetch to a linear address that translates to physical address in a memorypage that has the execute-disable bit set.An Execute Disable Bit page fault can occur at all privilege levels.
It can occur on anyinstruction fetch, including (but not limited to): near branches, far branches,CALL/RET/INT/IRET execution, sequential instruction fetches, and task switches. Theexecute-disable bit in the page translation mechanism is checked only when:••IA32_EFER.NXE = 1.The instruction translation look-aside buffer (ITLB) is loaded with a page that isnot already present in the ITLB.Vol. 3 4-47PROTECTION4-48 Vol. 3CHAPTER 5INTERRUPT AND EXCEPTION HANDLINGThis chapter describes the interrupt and exception-handling mechanism when operating in protected mode on an Intel 64 or IA-32 processor. Most of the informationprovided here also applies to interrupt and exception mechanisms used in realaddress, virtual-8086 mode, and 64-bit mode.Chapter 15, “8086 Emulation,” describes information specific to interrupt and exception mechanisms in real-address and virtual-8086 mode.
Section 5.14, “Exceptionand Interrupt Handling in 64-bit Mode,” describes information specific to interruptand exception mechanisms in IA-32e mode and 64-bit sub-mode.5.1INTERRUPT AND EXCEPTION OVERVIEWInterrupts and exceptions are events that indicate that a condition exists somewherein the system, the processor, or within the currently executing program or task thatrequires the attention of a processor. They typically result in a forced transfer ofexecution from the currently running program or task to a special software routine ortask called an interrupt handler or an exception handler.
The action taken by aprocessor in response to an interrupt or exception is referred to as servicing orhandling the interrupt or exception.Interrupts occur at random times during the execution of a program, in response tosignals from hardware. System hardware uses interrupts to handle events externalto the processor, such as requests to service peripheral devices. Software can alsogenerate interrupts by executing the INT n instruction.Exceptions occur when the processor detects an error condition while executing aninstruction, such as division by zero.
The processor detects a variety of error conditions including protection violations, page faults, and internal machine faults. Themachine-check architecture of the Pentium 4, Intel Xeon, P6 family, and Pentiumprocessors also permits a machine-check exception to be generated when internalhardware errors and bus errors are detected.When an interrupt is received or an exception is detected, the currently runningprocedure or task is suspended while the processor executes an interrupt or exception handler. When execution of the handler is complete, the processor resumesexecution of the interrupted procedure or task.
The resumption of the interruptedprocedure or task happens without loss of program continuity, unless recovery froman exception was not possible or an interrupt caused the currently running programto be terminated.This chapter describes the processor’s interrupt and exception-handling mechanism,when operating in protected mode. A description of the exceptions and the conditionsthat cause them to be generated is given at the end of this chapter.Vol. 3 5-1INTERRUPT AND EXCEPTION HANDLING5.2EXCEPTION AND INTERRUPT VECTORSTo aid in handling exceptions and interrupts, each architecturally defined exceptionand each interrupt condition requiring special handling by the processor is assigneda unique identification number, called a vector.
The processor uses the vectorassigned to an exception or interrupt as an index into the interrupt descriptor table(IDT). The table provides the entry point to an exception or interrupt handler (seeSection 5.10, “Interrupt Descriptor Table (IDT)”).The allowable range for vector numbers is 0 to 255. Vectors in the range 0 through31 are reserved by the Intel 64 and IA-32 architectures for architecture-definedexceptions and interrupts.
Not all of the vectors in this range have a currently definedfunction. The unassigned vectors in this range are reserved. Do not use the reservedvectors.Vectors in the range 32 to 255 are designated as user-defined interrupts and are notreserved by the Intel 64 and IA-32 architecture. These interrupts are generallyassigned to external I/O devices to enable those devices to send interrupts to theprocessor through one of the external hardware interrupt mechanisms (see Section5.3, “Sources of Interrupts”).Table 5-1 shows vector assignments for architecturally defined exceptions and for theNMI interrupt. This table gives the exception type (see Section 5.5, “Exception Classifications”) and indicates whether an error code is saved on the stack for the exception.
The source of each predefined exception and the NMI interrupt is also given.5.3SOURCES OF INTERRUPTSThe processor receives interrupts from two sources:••External (hardware generated) interrupts.Software-generated interrupts.5.3.1External InterruptsExternal interrupts are received through pins on the processor or through the localAPIC. The primary interrupt pins on Pentium 4, Intel Xeon, P6 family, and Pentiumprocessors are the LINT[1:0] pins, which are connected to the local APIC (seeChapter 8, “Advanced Programmable Interrupt Controller (APIC)”). When the localAPIC is enabled, the LINT[1:0] pins can be programmed through the APIC’s localvector table (LVT) to be associated with any of the processor’s exception or interruptvectors.When the local APIC is global/hardware disabled, these pins are configured as INTRand NMI pins, respectively.
Asserting the INTR pin signals the processor that anexternal interrupt has occurred. The processor reads from the system bus the interrupt vector number provided by an external interrupt controller, such as an 8259A5-2 Vol. 3INTERRUPT AND EXCEPTION HANDLING(see Section 5.2, “Exception and Interrupt Vectors”). Asserting the NMI pin signals anon-maskable interrupt (NMI), which is assigned to interrupt vector 2.Table 5-1. Protected-Mode Exceptions and InterruptsVectorNo.Mne- DescriptionmonicTypeErrorCodeSource0#DEDivide ErrorFaultNoDIV and IDIV instructions.1#DBRESERVEDFault/TrapNoFor Intel use only.2—NMI InterruptInterruptNoNonmaskable externalinterrupt.3#BPBreakpointTrapNoINT 3 instruction.4#OFOverflowTrapNoINTO instruction.5#BRBOUND Range ExceededFaultNoBOUND instruction.6#UDInvalid Opcode (UndefinedOpcode)FaultNoUD2 instruction or reservedopcode.17#NMDevice Not Available (NoMath Coprocessor)FaultNoFloating-point or WAIT/FWAITinstruction.8#DFDouble FaultAbortYes(zero)Any instruction that cangenerate an exception, an NMI,or an INTR.Coprocessor SegmentOverrun (reserved)FaultNoFloating-point instruction.2910#TSInvalid TSSFaultYesTask switch or TSS access.11#NPSegment Not PresentFaultYesLoading segment registers oraccessing system segments.12#SSStack-Segment FaultFaultYesStack operations and SSregister loads.13#GPGeneral ProtectionFaultYesAny memory reference andother protection checks.14#PFPage FaultFaultYesAny memory reference.15—(Intel reserved.
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