Volume 3A System Programming Guide_ Part 1 (794103), страница 54
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With these processors as well,exceptions and interrupts are not signaled until actual “in-order” execution of theinstructions. For a given code sample, the signaling of exceptions occurs uniformlywhen the code is executed on any family of IA-32 processors (except where newexceptions or new opcodes have been defined).5.7NONMASKABLE INTERRUPT (NMI)The nonmaskable interrupt (NMI) can be generated in either of two ways:••External hardware asserts the NMI pin.The processor receives a message on the system bus (Pentium 4 and Intel Xeonprocessors) or the APIC serial bus (P6 family and Pentium processors) with adelivery mode NMI.When the processor receives a NMI from either of these sources, the processorhandles it immediately by calling the NMI handler pointed to by interrupt vectornumber 2. The processor also invokes certain hardware conditions to insure that noother interrupts, including NMI interrupts, are received until the NMI handler hascompleted executing (see Section 5.7.1, “Handling Multiple NMIs”).Also, when an NMI is received from either of the above sources, it cannot be maskedby the IF flag in the EFLAGS register.5-8 Vol.
3INTERRUPT AND EXCEPTION HANDLINGIt is possible to issue a maskable hardware interrupt (through the INTR pin) to vector2 to invoke the NMI interrupt handler; however, this interrupt will not truly be an NMIinterrupt. A true NMI interrupt that activates the processor’s NMI-handling hardwarecan only be delivered through one of the mechanisms listed above.5.7.1Handling Multiple NMIsWhile an NMI interrupt handler is executing, the processor disables additional calls tothe NMI handler until the next IRET instruction is executed. This blocking of subsequent NMIs prevents stacking up calls to the NMI handler.
It is recommended that theNMI interrupt handler be accessed through an interrupt gate to disable maskablehardware interrupts (see Section 5.8.1, “Masking Maskable Hardware Interrupts”). Ifthe NMI handler is a virtual-8086 task with an IOPL of less than 3, an IRET instructionissued from the handler generates a general-protection exception (see Section15.2.7, “Sensitive Instructions”). In this case, the NMI is unmasked before thegeneral-protection exception handler is invoked.5.8ENABLING AND DISABLING INTERRUPTSThe processor inhibits the generation of some interrupts, depending on the state ofthe processor and of the IF and RF flags in the EFLAGS register, as described in thefollowing sections.5.8.1Masking Maskable Hardware InterruptsThe IF flag can disable the servicing of maskable hardware interrupts received on theprocessor’s INTR pin or through the local APIC (see Section 5.3.2, “Maskable Hardware Interrupts”).
When the IF flag is clear, the processor inhibits interrupts delivered to the INTR pin or through the local APIC from generating an internal interruptrequest; when the IF flag is set, interrupts delivered to the INTR or through the localAPIC pin are processed as normal external interrupts.The IF flag does not affect non-maskable interrupts (NMIs) delivered to the NMI pinor delivery mode NMI messages delivered through the local APIC, nor does it affectprocessor generated exceptions. As with the other flags in the EFLAGS register, theprocessor clears the IF flag in response to a hardware reset.The fact that the group of maskable hardware interrupts includes the reserved interrupt and exception vectors 0 through 32 can potentially cause confusion.
Architecturally, when the IF flag is set, an interrupt for any of the vectors from 0 through 32 canbe delivered to the processor through the INTR pin and any of the vectors from 16through 32 can be delivered through the local APIC. The processor will then generatean interrupt and call the interrupt or exception handler pointed to by the vectornumber.
So for example, it is possible to invoke the page-fault handler through theINTR pin (by means of vector 14); however, this is not a true page-fault exception. ItVol. 3 5-9INTERRUPT AND EXCEPTION HANDLINGis an interrupt. As with the INT n instruction (see Section 5.4.2, “Software-GeneratedExceptions”), when an interrupt is generated through the INTR pin to an exceptionvector, the processor does not push an error code on the stack, so the exceptionhandler may not operate correctly.The IF flag can be set or cleared with the STI (set interrupt-enable flag) and CLI(clear interrupt-enable flag) instructions, respectively. These instructions may beexecuted only if the CPL is equal to or less than the IOPL.
A general-protection exception (#GP) is generated if they are executed when the CPL is greater than the IOPL.(The effect of the IOPL on these instructions is modified slightly when the virtualmode extension is enabled by setting the VME flag in control register CR4: seeSection 15.3, “Interrupt and Exception Handling in Virtual-8086 Mode.” Behavior isalso impacted by the PVI flag: see Section 15.4, “Protected-Mode Virtual Interrupts.”The IF flag is also affected by the following operations:•The PUSHF instruction stores all flags on the stack, where they can be examinedand modified.
The POPF instruction can be used to load the modified flags backinto the EFLAGS register.•Task switches and the POPF and IRET instructions load the EFLAGS register;therefore, they can be used to modify the setting of the IF flag.•When an interrupt is handled through an interrupt gate, the IF flag is automatically cleared, which disables maskable hardware interrupts. (If an interrupt ishandled through a trap gate, the IF flag is not cleared.)See the descriptions of the CLI, STI, PUSHF, POPF, and IRET instructions in Chapter3, “Instruction Set Reference, A-M,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for a detailed description of the operationsthese instructions are allowed to perform on the IF flag.5.8.2Masking Instruction BreakpointsThe RF (resume) flag in the EFLAGS register controls the response of the processorto instruction-breakpoint conditions (see the description of the RF flag in Section 2.3,“System Flags and Fields in the EFLAGS Register”).When set, it prevents an instruction breakpoint from generating a debug exception(#DB); when clear, instruction breakpoints will generate debug exceptions.
Theprimary function of the RF flag is to prevent the processor from going into a debugexception loop on an instruction-breakpoint. See Section 18.3.1.1, “InstructionBreakpoint Exception Condition,” for more information on the use of this flag.5-10 Vol. 3INTERRUPT AND EXCEPTION HANDLING5.8.3Masking Exceptions and Interrupts When Switching StacksTo switch to a different stack segment, software often uses a pair of instructions, forexample:MOV SS, AXMOV ESP, StackTopIf an interrupt or exception occurs after the segment selector has been loaded intothe SS register but before the ESP register has been loaded, these two parts of thelogical address into the stack space are inconsistent for the duration of the interruptor exception handler.To prevent this situation, the processor inhibits interrupts, debug exceptions, andsingle-step trap exceptions after either a MOV to SS instruction or a POP to SSinstruction, until the instruction boundary following the next instruction is reached.All other faults may still be generated.
If the LSS instruction is used to modify thecontents of the SS register (which is the recommended method of modifying thisregister), this problem does not occur.5.9PRIORITY AMONG SIMULTANEOUS EXCEPTIONS ANDINTERRUPTSIf more than one exception or interrupt is pending at an instruction boundary, theprocessor services them in a predictable order. Table 5-2 shows the priority amongclasses of exception and interrupt sources.Table 5-2. Priority Among Simultaneous Exceptions and InterruptsPriority1 (Highest)DescriptionHardware Reset and Machine Checks- RESET- Machine Check2Trap on Task Switch- T flag in TSS is set3External Hardware Interventions- FLUSH- STOPCLK- SMI- INIT4Traps on the Previous Instruction- Breakpoints- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)Vol. 3 5-11INTERRUPT AND EXCEPTION HANDLINGTable 5-2.
Priority Among Simultaneous Exceptions and Interrupts (Contd.)5Nonmaskable Interrupts (NMI) 16Maskable Hardware Interrupts 17Code Breakpoint Fault8Faults from Fetching Next Instruction- Code-Segment Limit Violation- Code Page Fault9Faults from Decoding the Next Instruction- Instruction length > 15 bytes- Invalid Opcode- Coprocessor Not Available10 (Lowest)Faults on Executing an Instruction- Overflow- Bound error- Invalid TSS- Segment Not Present- Stack fault- General Protection- Data Page Fault- Alignment Check- x87 FPU Floating-point exception- SIMD floating-point exceptionNOTE:1.
The Intel486™ processor and earlier processors group nonmaskable and maskable interrupts inthe same priority class.While priority among these classes listed in Table 5-2 is consistent throughout thearchitecture, exceptions within each class are implementation-dependent and mayvary from processor to processor. The processor first services a pending exception orinterrupt from the class which has the highest priority, transferring execution to thefirst instruction of the handler. Lower priority exceptions are discarded; lower priorityinterrupts are held pending.
Discarded exceptions are re-generated when the interrupt handler returns execution to the point in the program or task where the exceptions and/or interrupts occurred.5.10INTERRUPT DESCRIPTOR TABLE (IDT)The interrupt descriptor table (IDT) associates each exception or interrupt vectorwith a gate descriptor for the procedure or task used to service the associated exception or interrupt. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors (in5-12 Vol.
3INTERRUPT AND EXCEPTION HANDLINGprotected mode). Unlike the GDT, the first entry of the IDT may contain a descriptor.To form an index into the IDT, the processor scales the exception or interrupt vectorby eight (the number of bytes in a gate descriptor). Because there are only 256 interrupt or exception vectors, the IDT need not contain more than 256 descriptors. It cancontain fewer than 256 descriptors, because descriptors are required only for theinterrupt and exception vectors that may occur.
All empty descriptor slots in the IDTshould have the present flag for the descriptor set to 0.The base addresses of the IDT should be aligned on an 8-byte boundary to maximizeperformance of cache line fills. The limit value is expressed in bytes and is added tothe base address to get the address of the last valid byte. A limit value of 0 results inexactly 1 valid byte. Because IDT entries are always eight bytes long, the limit shouldalways be one less than an integral multiple of eight (that is, 8N – 1).The IDT may reside anywhere in the linear address space. As shown in Figure 5-1,the processor locates the IDT using the IDTR register.
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