Volume 3A System Programming Guide_ Part 1 (794103), страница 59
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3INTERRUPT AND EXCEPTION HANDLINGSaved Instruction PointerThe saved contents of CS and EIP registers point to the floating-point instruction orthe WAIT/FWAIT instruction that generated the exception.Program State ChangeA program-state change does not accompany a device-not-available fault, becausethe instruction that generated the exception is not executed.If the EM flag is set, the exception handler can then read the floating-point instruction pointed to by the EIP and call the appropriate emulation routine.If the MP and TS flags are set or the TS flag alone is set, the exception handler cansave the context of the x87 FPU, clear the TS flag, and continue execution at theinterrupted floating-point or WAIT/FWAIT instruction.Vol. 3 5-37INTERRUPT AND EXCEPTION HANDLINGInterrupt 8—Double Fault Exception (#DF)Exception ClassAbort.DescriptionIndicates that the processor detected a second exception while calling an exceptionhandler for a prior exception.
Normally, when the processor detects another exception while trying to call an exception handler, the two exceptions can be handled serially. If, however, the processor cannot handle them serially, it signals the double-faultexception. To determine when two faults need to be signalled as a double fault, theprocessor divides the exceptions into three classes: benign exceptions, contributoryexceptions, and page faults (see Table 5-4).Table 5-4.
Interrupt and Exception ClassesClassVector NumberDescriptionBenign Exceptions andInterrupts12345679161718DebugNMI InterruptBreakpointOverflowBOUND Range ExceededInvalid OpcodeDevice Not AvailableCoprocessor Segment OverrunFloating-Point ErrorAlignment CheckMachine Check19AllAllSIMD floating-pointINT nINTRContributory Exceptions010111213Divide ErrorInvalid TSSSegment Not PresentStack FaultGeneral ProtectionPage Faults14Page FaultTable 5-5 shows the various combinations of exception classes that cause a doublefault to be generated.
A double-fault exception falls in the abort class of exceptions.The program or task cannot be restarted or resumed. The double-fault handler canbe used to collect diagnostic information about the state of the machine and/or, whenpossible, to shut the application and/or system down gracefully or restart thesystem.5-38 Vol. 3INTERRUPT AND EXCEPTION HANDLINGA segment or page fault may be encountered while prefetching instructions;however, this behavior is outside the domain of Table 5-5. Any further faults generated while the processor is attempting to transfer control to the appropriate faulthandler could still lead to a double-fault sequence.Table 5-5.
Conditions for Generating a Double FaultSecond ExceptionFirst ExceptionBenignContributoryPage FaultBenignHandle ExceptionsSeriallyHandle ExceptionsSeriallyHandle ExceptionsSeriallyContributoryHandle ExceptionsSeriallyGenerate a DoubleFaultHandle ExceptionsSeriallyPage FaultHandle ExceptionsSeriallyGenerate a DoubleFaultGenerate a Double FaultIf another exception occurs while attempting to call the double-fault handler, theprocessor enters shutdown mode.
This mode is similar to the state following execution of an HLT instruction. In this mode, the processor stops executing instructionsuntil an NMI interrupt, SMI interrupt, hardware reset, or INIT# is received. Theprocessor generates a special bus cycle to indicate that it has entered shutdownmode. Software designers may need to be aware of the response of hardware whenit goes into shutdown mode. For example, hardware may turn on an indicator light onthe front panel, generate an NMI interrupt to record diagnostic information, invokereset initialization, generate an INIT initialization, or generate an SMI.
If any eventsare pending during shutdown, they will be handled after an wake event from shutdown is processed (for example, A20M# interrupts).If a shutdown occurs while the processor is executing an NMI interrupt handler, thenonly a hardware reset can restart the processor. Likewise, if the shutdown occurswhile executing in SMM, a hardware reset must be used to restart the processor.Exception Error CodeZero.
The processor always pushes an error code of 0 onto the stack of the doublefault handler.Saved Instruction PointerThe saved contents of CS and EIP registers are undefined.Program State ChangeA program-state following a double-fault exception is undefined. The program or taskcannot be resumed or restarted. The only available action of the double-fault exception handler is to collect all possible context information for use in diagnostics andthen close the application and/or shut down or reset the processor.Vol. 3 5-39INTERRUPT AND EXCEPTION HANDLINGIf the double fault occurs when any portion of the exception handling machine stateis corrupted, the handler cannot be invoked and the processor must be reset.5-40 Vol.
3INTERRUPT AND EXCEPTION HANDLINGInterrupt 9—Coprocessor Segment OverrunException ClassAbort. (Intel reserved; do not use. Recent IA-32 processorsdo not generate this exception.)DescriptionIndicates that an Intel386 CPU-based systems with an Intel 387 math coprocessordetected a page or segment violation while transferring the middle portion of anIntel 387 math coprocessor operand. The P6 family, Pentium, and Intel486 processors do not generate this exception; instead, this condition is detected with a generalprotection exception (#GP), interrupt 13.Exception Error CodeNone.Saved Instruction PointerThe saved contents of CS and EIP registers point to the instruction that generated theexception.Program State ChangeA program-state following a coprocessor segment-overrun exception is undefined.
The program or task cannot be resumed or restarted. The only available actionof the exception handler is to save the instruction pointer and reinitialize the x87 FPUusing the FNINIT instruction.Vol. 3 5-41INTERRUPT AND EXCEPTION HANDLINGInterrupt 10—Invalid TSS Exception (#TS)Exception ClassFault.DescriptionIndicates that there was an error related to a TSS. Such an error might be detectedduring a task switch or during the execution of instructions that use information froma TSS. Table 5-6 shows the conditions that cause an invalid TSS exception to begenerated.Table 5-6.
Invalid TSS ConditionsError Code IndexInvalid ConditionTSS segment selector indexThe TSS segment limit is less than 67H for 32-bit TSS or less than2CH for 16-bit TSS.TSS segment selector indexDuring an IRET task switch, the TI flag in the TSS segment selectorindicates the LDT.TSS segment selector indexDuring an IRET task switch, the TSS segment selector exceedsdescriptor table limit.TSS segment selector indexDuring an IRET task switch, the busy flag in the TSS descriptorindicates an inactive task.TSS segment selector indexDuring an IRET task switch, an attempt to load the backlink limitfaults.TSS segment selector indexDuring an IRET task switch, the backlink is a NULL selector.TSS segment selector indexDuring an IRET task switch, the backlink points to a descriptorwhich is not a busy TSS.TSS segment selector indexThe new TSS descriptor is beyond the GDT limit.TSS segment selector indexThe new TSS descriptor is not writable.TSS segment selector indexStores to the old TSS encounter a fault condition.TSS segment selector indexThe old TSS descriptor is not writable for a jump or IRET taskswitch.TSS segment selector indexThe new TSS backlink is not writable for a call or exception taskswitch.TSS segment selector indexThe new TSS selector is null on an attempt to lock the new TSS.TSS segment selector indexThe new TSS selector has the TI bit set on an attempt to lock thenew TSS.TSS segment selector indexThe new TSS descriptor is not an available TSS descriptor on anattempt to lock the new TSS.LDT segment selector indexLDT or LDT not present.5-42 Vol.
3INTERRUPT AND EXCEPTION HANDLINGTable 5-6. Invalid TSS Conditions (Contd.)Error Code IndexInvalid ConditionStack segment selectorindexThe stack segment selector exceeds descriptor table limit.Stack segment selectorindexThe stack segment selector is NULL.Stack segment selectorindexThe stack segment descriptor is a non-data segment.Stack segment selectorindexThe stack segment is not writable.Stack segment selectorindexThe stack segment DPL != CPL.Stack segment selectorindexThe stack segment selector RPL != CPL.Code segment selectorindexThe code segment selector exceeds descriptor table limit.Code segment selectorindexThe code segment selector is NULL.Code segment selectorindexThe code segment descriptor is not a code segment type.Code segment selectorindexThe nonconforming code segment DPL != CPL.Code segment selectorindexThe conforming code segment DPL is greater than CPL.Data segment selector index The data segment selector exceeds the descriptor table limit.Data segment selector index The data segment descriptor is not a readable code or data type.Data segment selector indexThe data segment descriptor is a nonconforming code type and RPL> DPL.Data segment selector index The data segment descriptor is a nonconforming code type and CPL> DPL.TSS segment selector indexThe TSS segment selector is NULL for LTR.TSS segment selector indexThe TSS segment selector has the TI bit set for LTR.TSS segment selector indexThe TSS segment descriptor/upper descriptor is beyond the GDTsegment limit.TSS segment selector indexThe TSS segment descriptor is not an available TSS type.TSS segment selector indexThe TSS segment descriptor is an available 286 TSS type in IA-32emode.Vol.
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