Volume 3A System Programming Guide_ Part 1 (794103), страница 66
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Afterwards, the contents of the task registerare changed implicitly when a task switch occurs.The STR (store task register) instruction stores the visible portion of the task registerin a general-purpose register or memory. This instruction can be executed by coderunning at any privilege level in order to identify the currently running task. However,it is normally used only by operating system software.On power up or reset of the processor, segment selector and base address are set tothe default value of 0; the limit is set to FFFFH.TSS+Visible PartTaskRegisterSelectorInvisible PartBase AddressSegment LimitGDTTSS Descriptor0Figure 6-5. Task Register6-10 Vol. 3TASK MANAGEMENT6.2.5Task-Gate DescriptorA task-gate descriptor provides an indirect, protected reference to a task (seeFigure 6-6).
It can be placed in the GDT, an LDT, or the IDT. The TSS segmentselector field in a task-gate descriptor points to a TSS descriptor in the GDT. The RPLin this segment selector is not used.The DPL of a task-gate descriptor controls access to the TSS descriptor during a taskswitch. When a program or procedure makes a call or jump to a task through a taskgate, the CPL and the RPL field of the gate selector pointing to the task gate must beless than or equal to the DPL of the task-gate descriptor. Note that when a task gateis used, the DPL of the destination TSS descriptor is not used.3116 15 14 13 12 11Reserved31PDPLTypeDPLPTYPEReserved40 0 1 0 116 15TSS Segment Selector08 70Reserved0Descriptor Privilege LevelSegment PresentSegment TypeFigure 6-6.
Task-Gate DescriptorA task can be accessed either through a task-gate descriptor or a TSS descriptor.Both of these structures satisfy the following needs:•Need for a task to have only one busy flag — Because the busy flag for a taskis stored in the TSS descriptor, each task should have only one TSS descriptor.There may, however, be several task gates that reference the same TSSdescriptor.•Need to provide selective access to tasks — Task gates fill this need, becausethey can reside in an LDT and can have a DPL that is different from the TSSdescriptor's DPL. A program or procedure that does not have sufficient privilegeto access the TSS descriptor for a task in the GDT (which usually has a DPL of 0)may be allowed access to the task through a task gate with a higher DPL.
Taskgates give the operating system greater latitude for limiting access to specifictasks.•Need for an interrupt or exception to be handled by an independent task— Task gates may also reside in the IDT, which allows interrupts and exceptionsVol. 3 6-11TASK MANAGEMENTto be handled by handler tasks. When an interrupt or exception vector points toa task gate, the processor switches to the specified task.Figure 6-7 illustrates how a task gate in an LDT, a task gate in the GDT, and a taskgate in the IDT can all point to the same task.LDTGDTTSSTask GateTask GateTSS DescriptorIDTTask GateFigure 6-7.
Task Gates Referencing the Same Task6.3TASK SWITCHINGThe processor transfers execution to another task in one of four cases:•The current program, task, or procedure executes a JMP or CALL instruction to aTSS descriptor in the GDT.•The current program, task, or procedure executes a JMP or CALL instruction to atask-gate descriptor in the GDT or the current LDT.6-12 Vol. 3TASK MANAGEMENT••An interrupt or exception vector points to a task-gate descriptor in the IDT.The current task executes an IRET when the NT flag in the EFLAGS register is set.JMP, CALL, and IRET instructions, as well as interrupts and exceptions, are all mechanisms for redirecting a program. The referencing of a TSS descriptor or a task gate(when calling or jumping to a task) or the state of the NT flag (when executing anIRET instruction) determines whether a task switch occurs.The processor performs the following operations when switching to a new task:1.
Obtains the TSS segment selector for the new task as the operand of the JMP orCALL instruction, from a task gate, or from the previous task link field (for a taskswitch initiated with an IRET instruction).2. Checks that the current (old) task is allowed to switch to the new task. Dataaccess privilege rules apply to JMP and CALL instructions.
The CPL of the current(old) task and the RPL of the segment selector for the new task must be less thanor equal to the DPL of the TSS descriptor or task gate being referenced.Exceptions, interrupts (except for interrupts generated by the INT n instruction),and the IRET instruction are permitted to switch tasks regardless of the DPL ofthe destination task-gate or TSS descriptor. For interrupts generated by the INT ninstruction, the DPL is checked.3. Checks that the TSS descriptor of the new task is marked present and has a validlimit (greater than or equal to 67H).4. Checks that the new task is available (call, jump, exception, or interrupt) or busy(IRET return).5.
Checks that the current (old) TSS, new TSS, and all segment descriptors used inthe task switch are paged into system memory.6. If the task switch was initiated with a JMP or IRET instruction, the processorclears the busy (B) flag in the current (old) task’s TSS descriptor; if initiated witha CALL instruction, an exception, or an interrupt: the busy (B) flag is left set.(See Table 6-2.)7. If the task switch was initiated with an IRET instruction, the processor clears theNT flag in a temporarily saved image of the EFLAGS register; if initiated with aCALL or JMP instruction, an exception, or an interrupt, the NT flag is leftunchanged in the saved EFLAGS image.8.
Saves the state of the current (old) task in the current task’s TSS. The processorfinds the base address of the current TSS in the task register and then copies thestates of the following registers into the current TSS: all the general-purposeregisters, segment selectors from the segment registers, the temporarily savedimage of the EFLAGS register, and the instruction pointer register (EIP).9. If the task switch was initiated with a CALL instruction, an exception, or aninterrupt, the processor will set the NT flag in the EFLAGS loaded from the newtask.
If initiated with an IRET instruction or JMP instruction, the NT flag will reflectthe state of NT in the EFLAGS loaded from the new task (see Table 6-2).Vol. 3 6-13TASK MANAGEMENT10. If the task switch was initiated with a CALL instruction, JMP instruction, anexception, or an interrupt, the processor sets the busy (B) flag in the new task’sTSS descriptor; if initiated with an IRET instruction, the busy (B) flag is left set.11. Loads the task register with the segment selector and descriptor for the newtask's TSS.12. The TSS state is loaded into the processor. This includes the LDTR register, thePDBR (control register CR3), the EFLAGS registers, the EIP register, the generalpurpose registers, and the segment selectors.
Note that a fault during the load ofthis state may corrupt architectural state.13. The descriptors associated with the segment selectors are loaded and qualified.Any errors associated with this loading and qualification occur in the context ofthe new task.NOTESIf all checks and saves have been carried out successfully, theprocessor commits to the task switch. If an unrecoverable erroroccurs in steps 1 through 11, the processor does not complete thetask switch and insures that the processor is returned to its stateprior to the execution of the instruction that initiated the task switch.If an unrecoverable error occurs in step 12, architectural state maybe corrupted, but an attempt will be made to handle the error in theprior execution environment.
If an unrecoverable error occurs afterthe commit point (in step 13), the processor completes the taskswitch (without performing additional access and segment availability checks) and generates the appropriate exception prior tobeginning execution of the new task.If exceptions occur after the commit point, the exception handlermust finish the task switch itself before allowing the processor tobegin executing the new task. See Chapter 5, “Interrupt 10—InvalidTSS Exception (#TS),” for more information about the affect ofexceptions on a task when they occur after the commit point of a taskswitch.14. Begins executing the new task.
(To an exception handler, the first instruction ofthe new task appears not to have been executed.)The state of the currently executing task is always saved when a successful taskswitch occurs. If the task is resumed, execution starts with the instruction pointed toby the saved EIP value, and the registers are restored to the values they held whenthe task was suspended.When switching tasks, the privilege level of the new task does not inherit its privilegelevel from the suspended task.
The new task begins executing at the privilege levelspecified in the CPL field of the CS register, which is loaded from the TSS. Becausetasks are isolated by their separate address spaces and TSSs and because privilege6-14 Vol. 3TASK MANAGEMENTrules control access to a TSS, software does not need to perform explicit privilegechecks on a task switch.Table 6-1 shows the exception conditions that the processor checks for whenswitching tasks. It also shows the exception that is generated for each check if anerror is detected and the segment that the error code references. (The order of thechecks in the table is the order used in the P6 family processors. The exact order ismodel specific and may be different for other IA-32 processors.) Exception handlersdesigned to handle these exceptions may be subject to recursive calls if they attemptto reload the segment selector that generated the exception.
The cause of the exception (or the first of multiple causes) should be fixed before reloading the selector.Table 6-1. Exception Conditions Checked During a Task SwitchCondition CheckedException1Error CodeReference2Segment selector for a TSS descriptor referencesthe GDT and is within the limits of the table.#GPNew Task’s TSSTSS descriptor is present in memory.#NPNew Task’s TSSTSS descriptor is not busy (for task switch initiatedby a call, interrupt, or exception).#GP (for JMP, CALL,INT)Task’s back-link TSSTSS descriptor is not busy (for task switch initiatedby an IRET instruction).#TS (for IRET)New Task’s TSS#TS (for IRET)TSS segment limit greater than or equal to 108 (for #TS32-bit TSS) or 44 (for 16-bit TSS).New Task’s TSSRegisters are loaded from the values in the TSS.LDT segment selector of new task is valid 3.#TSNew Task’s LDTCode segment DPL matches segment selector RPL.#TSNew Code SegmentSS segment selector is valid 2.#TSNew Stack SegmentStack segment is present in memory.#SSNew Stack SegmentStack segment DPL matches CPL.#TSNew stack segmentLDT of new task is present in memory.#TSNew Task’s LDTCS segment selector is valid 3.#TSNew Code SegmentCode segment is present in memory.#NPNew Code Segment#TSNew Stack SegmentStack segment DPL matches selector RPL.DS, ES, FS, and GS segment selectors are validDS, ES, FS, and GS segments are readable.3.#TSNew Data Segment#TSNew Data SegmentVol.
3 6-15TASK MANAGEMENTTable 6-1. Exception Conditions Checked During a Task Switch (Contd.)Condition CheckedException1Error CodeReference2DS, ES, FS, and GS segments are present in memory. #NPNew Data SegmentDS, ES, FS, and GS segment DPL greater than orequal to CPL (unless these areconforming segments).New Data Segment#TSNOTES:1. #NP is segment-not-present exception, #GP is general-protection exception, #TS is invalid-TSSexception, and #SS is stack-fault exception.2. The error code contains an index to the segment descriptor referenced in this column.3.
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