Volume 3A System Programming Guide_ Part 1 (794103), страница 70
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IA-32processors exhibit model-specific behavior when executing self-modified code,depending upon how far ahead of the current execution pointer the code has beenmodified.As processor microarchitectures become more complex and start to speculativelyexecute code ahead of the retirement point (as in P6 and more recent processorfamilies), the rules regarding which code should execute, pre- or post-modification,become blurred.
To write self-modifying code and ensure that it is compliant withcurrent and future versions of the IA-32 architectures, use one of the followingcoding options:(* OPTION 1 *)Store modified code (as data) into code segment;Jump to new code or an intermediate location;Execute new code;(* OPTION 2 *)Store modified code (as data) into code segment;Execute a serializing instruction; (* For example, CPUID instruction *)Execute new code;The use of one of these options is not required for programs intended to run on thePentium or Intel486 processors, but are recommended to insure compatibility withthe P6 and more recent processor families.Self-modifying code will execute at a lower level of performance than non-self-modifying or normal code. The degree of the performance deterioration will depend uponthe frequency of modification and specific characteristics of the code.7-6 Vol.
3MULTIPLE-PROCESSOR MANAGEMENTThe act of one processor writing data into the currently executing code segment of asecond processor with the intent of having the second processor execute that data ascode is called cross-modifying code.
As with self-modifying code, IA-32 processorsexhibit model-specific behavior when executing cross-modifying code, dependingupon how far ahead of the executing processors current execution pointer the codehas been modified.To write cross-modifying code and insure that it is compliant with current and futureversions of the IA-32 architecture, the following processor synchronization algorithmmust be implemented:(* Action of Modifying Processor *)Memory_Flag ← 0; (* Set Memory_Flag to value other than 1 *)Store modified code (as data) into code segment;Memory_Flag ← 1;(* Action of Executing Processor *)WHILE (Memory_Flag ≠ 1)Wait for code to update;ELIHW;Execute serializing instruction; (* For example, CPUID instruction *)Begin executing modified code;(The use of this option is not required for programs intended to run on the Intel486processor, but is recommended to insure compatibility with the Pentium 4, IntelXeon, P6 family, and Pentium processors.)Like self-modifying code, cross-modifying code will execute at a lower level of performance than non-cross-modifying (normal) code, depending upon the frequency ofmodification and specific characteristics of the code.The restrictions on self-modifying code and cross-modifying code also apply to theIntel 64 architecture.7.1.4Effects of a LOCK Operation on Internal Processor CachesFor the Intel486 and Pentium processors, the LOCK# signal is always asserted on thebus during a LOCK operation, even if the area of memory being locked is cached inthe processor.For the P6 and more recent processor families, if the area of memory being lockedduring a LOCK operation is cached in the processor that is performing the LOCK operation as write-back memory and is completely contained in a cache line, theprocessor may not assert the LOCK# signal on the bus.
Instead, it will modify thememory location internally and allow it’s cache coherency mechanism to insure thatthe operation is carried out atomically. This operation is called “cache locking.” Thecache coherency mechanism automatically prevents two or more processors thatVol. 3 7-7MULTIPLE-PROCESSOR MANAGEMENThave cached the same area of memory from simultaneously modifying data in thatarea.7.2MEMORY ORDERINGThe term memory ordering refers to the order in which the processor issues reads(loads) and writes (stores) through the system bus to system memory. The Intel 64and IA-32 architectures support several memory ordering models depending on theimplementation of the architecture.
For example, the Intel386 processor enforcesprogram ordering (generally referred to as strong ordering), where reads andwrites are issued on the system bus in the order they occur in the instruction streamunder all circumstances.To allow optimizing of instruction execution, the IA-32 architecture allows departuresfrom strong-ordering model called processor ordering in Pentium 4, Intel Xeon,and P6 family processors. These processor-ordering variations allow performanceenhancing operations such as allowing reads to go ahead of buffered writes. The goalof any of these variations is to increase instruction execution speeds, while maintaining memory coherency, even in multiple-processor systems.The following sections describe memory ordering models used by Intel486, Pentium,Intel Core 2 Duo, Intel Core Duo, Pentium 4, Intel Xeon, and P6 family processors.7.2.1Memory Ordering in the Intel® Pentium® and Intel486™ProcessorsThe Pentium and Intel486 processors follow the processor-ordered memory model;however, they operate as strongly-ordered processors under most circumstances.Reads and writes always appear in programmed order at the system bus—except forthe following situation where processor ordering is exhibited.
Read misses arepermitted to go ahead of buffered writes on the system bus when all the bufferedwrites are cache hits and, therefore, are not directed to the same address beingaccessed by the read miss.In the case of I/O operations, both reads and writes always appear in programmedorder.Software intended to operate correctly in processor-ordered processors (such as thePentium 4, Intel Xeon, and P6 family processors) should not depend on the relativelystrong ordering of the Pentium or Intel486 processors. Instead, it should insure thataccesses to shared variables that are intended to control concurrent executionamong processors are explicitly required to obey program ordering through the useof appropriate locking or serializing operations (see Section 7.2.4, “Strengthening orWeakening the Memory Ordering Model”).7-8 Vol.
3MULTIPLE-PROCESSOR MANAGEMENT7.2.2Memory Ordering in P6 and More Recent Processor FamiliesThe Intel Core 2 Duo, Intel Core Duo, Pentium 4, and P6 family processors also use aprocessor-ordered memory ordering model that can be further defined as “writeordered with store-buffer forwarding.” This model can be characterized as follows.In a single-processor system for memory regions defined as write-back cacheable,the following ordering rules apply:1. Reads can be carried out speculatively and in any order.2.
Reads can pass buffered writes, but the processor is self-consistent.3. Writes to memory are always carried out in program order, with the exception ofwrites executed with the CLFLUSH instruction and streaming stores (writes)executed with the non-temporal move instructions (MOVNTI, MOVNTQ,MOVNTDQ, MOVNTPS, and MOVNTPD).4. Writes can be buffered.5. Writes are not performed speculatively; they are only performed for instructionsthat have actually been retired.6. Data from buffered writes can be forwarded to waiting reads within the processor.7.
Reads or writes cannot pass (be carried out ahead of) I/O instructions, lockedinstructions, or serializing instructions.8. Reads cannot pass LFENCE and MFENCE instructions.9. Writes cannot pass SFENCE and MFENCE instructions.The second rule allows a read to pass a write. However, if the write is to the samememory location as the read, the processor’s internal “snooping” mechanism willdetect the conflict and update the cached read before the processor executes theinstruction that uses the value.The sixth rule constitutes an exception to an otherwise write ordered model. Notethat the term “write ordered with store-buffer forwarding” (introduced at the beginning of this section) refers to the combined effects of rules 2 and 6.In a multiple-processor system, the following ordering rules apply:•Individual processors use the same ordering rules as in a single-processorsystem.••Writes by a single processor are observed in the same order by all processors.Writes from the individual processors on the system bus are NOT ordered withrespect to each other.See the example in Figure 7-1.
Consider three processors in a system and eachprocessor performs three writes, one to each of three defined locations (A, B, and C).Individually, the processors perform the writes in the same program order, butbecause of bus arbitration and other memory access mechanisms, the order that thethree processors write the individual memory locations can differ each time theVol. 3 7-9MULTIPLE-PROCESSOR MANAGEMENTrespective code sequences are executed on the processors. The final values in location A, B, and C would possibly vary on each execution of the write sequence.The processor-ordering model described in this section is virtually identical to thatused by the Pentium and Intel486 processors.
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