Volume 3A System Programming Guide_ Part 1 (794103), страница 74
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This is the APIC ID reported byCPUID.1:EBX[31:24] and may be different from the current value read from thelocal APIC. Use the initial APIC ID to determine the topological relationshipbetween logical processors.Bits in the initial APIC ID can be interpreted using several bit masks. Each bitmask can be used to extract an identifier to represent a hierarchical level of the7-22 Vol. 3MULTIPLE-PROCESSOR MANAGEMENTmulti-threading resource topology in an MP system (See Section 7.10.1, “Hierarchical Mapping of Shared Resources”). The initial APIC ID may consist of up tofour bit-fields. In a non-clustered MP system, the field consists of up to three bitfields.Figure 7-2 shows two examples of APIC ID bit fields in earlier single-core processors.In single-core Intel Xeon processors, the APIC ID assigned to a logical processorduring power-up and initialization is 8 bits.
Bits 2:1 form a 2-bit physical packageidentifier (which can also be thought of as a socket identifier). In systems thatconfigure physical processors in clusters, bits 4:3 form a 2-bit cluster ID. Bit 0 is usedin the Intel Xeon processor MP to identify the two logical processors within thepackage (see Section 7.10.2, “Identifying Logical Processors in an MP System”).
ForIntel Xeon processors that do not support Intel Hyper-Threading Technology, bit 0 isalways set to 0; for Intel Xeon processors supporting Hyper-Threading Technology,bit 0 performs the same function as it does for Intel Xeon processor MP.For more recent multi-core processors, see Section 7.10.1, “Hierarchical Mapping ofShared Resources” for a complete description of the topological relationshipsbetween logical processors and bit field locations within an initial APIC ID across Intel64 and IA-32 processor families.Note the number of bit fields and the width of bit-fields are dependent on processorand platform hardware capabilities. Software should determine these at runtime.When initial APIC IDs are assigned to logical processors, the value of APIC IDassigned to a logical processor will respect the bit-field boundaries correspondingcore, physical package, etc.
Additional examples of the bit fields in the initial APIC IDof multi-threading capable systems are shown in Section 7.10.APIC ID Format for Intel Xeon Processors thatdo not Support Hyper-Threading Technology754321Reserved00ClusterProcessor IDAPIC ID Format for P6 Family Processors743210ReservedClusterProcessor IDFigure 7-2. Interpretation of APIC ID in Early MP SystemsVol. 3 7-23MULTIPLE-PROCESSOR MANAGEMENTFor P6 family processors, the APIC ID that is assigned to a processor during powerup and initialization is 4 bits (see Figure 7-2).
Here, bits 0 and 1 form a 2-bitprocessor (or socket) identifier and bits 2 and 3 form a 2-bit cluster ID.7.6HYPER-THREADING AND MULTI-CORE TECHNOLOGYHyper-Threading Technology and multi-core technology are extensions to Intel 64and IA-32 architectures that enable a single physical processor to execute two ormore separate code streams (called threads) concurrently. In Hyper-Threading Technology, a single processor core provides two logical processors that share executionresources (see Section 7.8, “Intel® Hyper-Threading Technology Architecture”).
Inmulti-core technology, a physical processor package provides two or more processorcores. Both configurations require chipsets and a BIOS that support the technologies.Software should not rely on processor names to determine whether a processorsupports Hyper-Threading Technology or multi-core technology. Use the CPUIDinstruction to determine processor capability (see Section 7.7.2, “Initializing MultiCore Processors”).7.7DETECTING HARDWARE MULTI-THREADINGSUPPORT AND TOPOLOGYUse the CPUID instruction to detect the presence of hardware multi-threadingsupport in a physical processor.
The following can be interpreted:•Hardware Multi-Threading feature flag (CPUID.1:EDX[28] = 1) —Indicates when set that the physical package is capable of supporting HyperThreading Technology and/or multiple cores.•Logical processors per Package (CPUID.1:EBX[23:16]) — Indicates themaximum number of logical processors in a physical package.
This representsthe hardware capability as the processor has been manufactured.2•Cores per Package3 (CPUID.(EAX=4, ECX=04):EAX[31:26] + 1 = Y) —Indicates the maximum number of processor cores (Y) in the physical package2. Operating system and BIOS may implement features that reduce the number of logical processors available in a platform to applications at runtime to less than the number of physical packages times the number of hardware-capable logical processors per package.3. Software must check CPUID for its support of leaf 4 when implementing support for multi-core.
IfCPUID leaf 4 is not available at runtime, software should handle the situation as if there is onlyone core per package.4. Maximum number of cores in the physical package must be queried by executing CPUID withEAX=4 and a valid ECX input value. Valid ECX input values start from 0.7-24 Vol. 3MULTIPLE-PROCESSOR MANAGEMENTThe CPUID feature flag may indicate support for hardware multi-threading when onlyone logical processor available in the package. In this case, the decimal value represented by bits 16 through 23 in the EBX register will have a value of 1.Software should note that the number of logical processors enabled by system software may be less than the value of “logical processors per package”.
Similarly, thenumber of cores enabled by system software may be less than the value of “cores perpackage”.7.7.1Initializing ProcessorsSupporting Hyper-Threading TechnologyThe initialization process for an MP system that contains processors supportingHyper-Threading Technology is the same as for conventional MP systems (seeSection 7.5, “Multiple-Processor (MP) Initialization”). One logical processor in thesystem is selected as the BSP and other processors (or logical processors) are designated as APs. The initialization process is identical to that described in Section 7.5.3,“MP Initialization Protocol Algorithm for Intel Xeon Processors,” and Section 7.5.4,“MP Initialization Example.”During initialization, each logical processor is assigned an APIC ID that is stored inthe local APIC ID register for each logical processor.
If two or more processorssupporting Hyper-Threading Technology are present, each logical processor on thesystem bus is assigned a unique ID (see Section 7.10.2, “Identifying Logical Processors in an MP System”). Once logical processors have APIC IDs, software communicates with them by sending APIC IPI messages.7.7.2Initializing Multi-Core ProcessorsThe initialization process for an MP system that contains multi-core Intel 64 or IA-32processors is the same as for conventional MP systems (see Section 7.5, “MultipleProcessor (MP) Initialization”). A logical processor in one core is selected as the BSP;other logical processors are designated as APs.During initialization, each logical processor is assigned an APIC ID.
Once logicalprocessors have APIC IDs, software may communicate with them by sending APICIPI messages.7.7.3Executing Multiple Threads on an Intel® 64 or IA-32Processor Supporting Hardware Multi-ThreadingUpon completing the operating system boot-up procedure, the bootstrap processor(BSP) executes operating system code. Other logical processors are placed in thehalt state. To execute a code stream (thread) on a halted logical processor, the operating system issues an interprocessor interrupt (IPI) addressed to the halted logicalVol.
3 7-25MULTIPLE-PROCESSOR MANAGEMENTprocessor. In response to the IPI, the processor wakes up and begins executing thethread identified by the interrupt vector received as part of the IPI.To manage execution of multiple threads on logical processors, an operating systemcan use conventional symmetric multiprocessing (SMP) techniques. For example, theoperating-system can use a time-slice or load balancing mechanism to periodicallyinterrupt each of the active logical processors. Upon interrupting a logical processor,the operating system checks its run queue for a thread waiting to be executed anddispatches the thread to the interrupted logical processor.7.7.4Handling Interrupts on an IA-32 Processor SupportingHardware Multi-ThreadingInterrupts are handled on processors supporting Hyper-Threading Technology asthey are on conventional MP systems.
External interrupts are received by the I/OAPIC, which distributes them as interrupt messages to specific logical processors(see Figure 7-3).Logical processors can also send IPIs to other logical processors by writing to the ICRregister of its local APIC (see Section 8.6, “Issuing Interprocessor Interrupts”). Thisalso applies to dual-core processors.7-26 Vol. 3MULTIPLE-PROCESSOR MANAGEMENTIntel Processor withIntel Processor withHyper-Threading Technology Hyper-Threading TechnologyLogicalLogicalProcessor 0 Processor 1LogicalLogicalProcessor 0 Processor 1Processor CoreProcessor CoreLocal APIC Local APICLocal APIC Local APICBus InterfaceBus InterfaceIPIsInterruptMessagesInterruptMessagesIPIsInterrupt MessagesBridgePCII/O APICExternalInterruptsSystem Chip SetFigure 7-3.
Local APICs and I/O APIC in MP System Supporting HT Technology7.8INTEL® HYPER-THREADING TECHNOLOGYARCHITECTUREFigure 7-4 shows a generalized view of an Intel processor supporting HyperThreading Technology, using the original Intel Xeon processor MP as an example.This implementation of the Hyper-Threading Technology consists of two logicalprocessors (each represented by a separate architectural state) which share theprocessor’s execution engine and the bus interface. Each logical processor also hasits own advanced programmable interrupt controller (APIC).Vol.
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