Volume 3A System Programming Guide_ Part 1 (794103), страница 72
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Nothing can pass a serializing instruction anda serializing instruction cannot pass any other instruction (read, write, instructionfetch, or I/O). For example, CPUID can be executed at any privilege level to serializeinstruction execution with no effect on program flow, except that the EAX, EBX, ECX,and EDX registers are modified.1. MOV CR8 is not defined architecturally as a serializing instruction.7-14 Vol. 3MULTIPLE-PROCESSOR MANAGEMENTThe following instructions are memory ordering instructions, not serializing instructions. These drain the data memory subsystem.
They do not effect the instructionexecution stream:•Non-privileged memory ordering instructions — SFENCE, LFENCE, andMFENCE.The SFENCE, LFENCE, and MFENCE instructions provide more granularity in controlling the serialization of memory loads and stores (see Section 7.2.4, “Strengtheningor Weakening the Memory Ordering Model”).The following additional information is worth noting regarding serializing instructions:•The processor does not writeback the contents of modified data in its data cacheto external memory when it serializes instruction execution. Software can forcemodified data to be written back by executing the WBINVD instruction, which is aserializing instruction. It should be noted that frequent use of the WBINVDinstruction will seriously reduce system performance.•When an instruction is executed that enables or disables paging (that is, changesthe PG flag in control register CR0), the instruction should be followed by a jumpinstruction.
The target instruction of the jump instruction is fetched with the newsetting of the PG flag (that is, paging is enabled or disabled), but the jumpinstruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon,and P6 family processors do not require the jump operation following the move toregister CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon,or P6 family processor to write to CR0 is completely serializing). However, tomaintain backwards and forward compatibility with code written to run on otherIA-32 processors, it is recommended that the jump operation be performed.•Whenever an instruction is executed to change the contents of CR3 while pagingis enabled, the next instruction is fetched using the translation tables thatcorrespond to the new value of CR3.
Therefore the next instruction and thesequentially following instructions should have a mapping based upon the newvalue of CR3. (Global entries in the TLBs are not invalidated, see Section 10.9,“Invalidating the Translation Lookaside Buffers (TLBs)”.)•The Pentium processor and more recent processor families use branch-predictiontechniques to improve performance by prefetching the destination of a branchinstruction before the branch instruction is executed. Consequently, instructionexecution is not deterministically serialized when a branch instruction isexecuted.7.5MULTIPLE-PROCESSOR (MP) INITIALIZATIONThe IA-32 architecture (beginning with the P6 family processors) defines a multipleprocessor (MP) initialization protocol called the Multiprocessor Specification Version1.4.
This specification defines the boot protocol to be used by IA-32 processors inVol. 3 7-15MULTIPLE-PROCESSOR MANAGEMENTmultiple-processor systems. (Here, multiple processors is defined as two or moreprocessors.) The MP initialization protocol has the following important features:•It supports controlled booting of multiple processors without requiring dedicatedsystem hardware.•It allows hardware to initiate the booting of a system without the need for adedicated signal or a predefined boot processor.•It allows all IA-32 processors to be booted in the same manner, including thosesupporting Hyper-Threading Technology.•The MP initialization protocol also applies to MP systems using Intel 64processors.The mechanism for carrying out the MP initialization protocol differs depending onthe IA-32 processor family, as follows:•For P6 family processors — The selection of the BSP and APs (see Section7.5.1, “BSP and AP Processors”) is handled through arbitration on the APIC bus,using BIPI and FIPI messages.
See Appendix C, “MP Initialization For P6 FamilyProcessors,” for a complete discussion of MP initialization for P6 familyprocessors.•Intel Xeon processors with family, model, and stepping IDs up to F09H —The selection of the BSP and APs (see Section 7.5.1, “BSP and AP Processors”) ishandled through arbitration on the system bus, using BIPI and FIPI messages(see Section 7.5.3, “MP Initialization Protocol Algorithm forIntel Xeon Processors”).•Intel Xeon processors with family, model, and stepping IDs of F0AH andbeyond, 6E0H and beyond, 6F0H and beyond — The selection of the BSP andAPs is handled through a special system bus cycle, without using BIPI and FIPImessage arbitration (see Section 7.5.3, “MP Initialization Protocol Algorithm forIntel Xeon Processors”).The family, model, and stepping ID for a processor is given in the EAX register whenthe CPUID instruction is executed with a value of 1 in the EAX register.7.5.1BSP and AP ProcessorsThe MP initialization protocol defines two classes of processors: the bootstrapprocessor (BSP) and the application processors (APs).
Following a power-up orRESET of an MP system, system hardware dynamically selects one of the processorson the system bus as the BSP. The remaining processors are designated as APs.As part of the BSP selection mechanism, the BSP flag is set in the IA32_APIC_BASEMSR (see Figure 8-5) of the BSP, indicating that it is the BSP. This flag is cleared forall other processors.The BSP executes the BIOS’s boot-strap code to configure the APIC environment,sets up system-wide data structures, and starts and initializes the APs. When the BSP7-16 Vol.
3MULTIPLE-PROCESSOR MANAGEMENTand APs are initialized, the BSP then begins executing the operating-system initialization code.Following a power-up or reset, the APs complete a minimal self-configuration, thenwait for a startup signal (a SIPI message) from the BSP processor. Upon receiving aSIPI message, an AP executes the BIOS AP configuration code, which ends with theAP being placed in halt state.For Intel 64 and IA-32 processors supporting Hyper-Threading Technology, the MPinitialization protocol treats each of the logical processors on the system bus as aseparate processor (with a unique APIC ID).
During boot-up, one of the logicalprocessors is selected as the BSP and the remainder of the logical processors aredesignated as APs.7.5.2MP Initialization Protocol Requirements and Restrictionsfor Intel Xeon ProcessorsThe MP initialization protocol imposes the following requirements and restrictions onthe system:•The MP protocol is executed only after a power-up or RESET. If the MP protocolhas completed and a BSP is chosen, subsequent INITs (either to a specificprocessor or system wide) do not cause the MP protocol to be repeated. Instead,each logical processor examines its BSP flag (in the IA32_APIC_BASE MSR) todetermine whether it should execute the BIOS boot-strap code (if it is the BSP) orenter a wait-for-SIPI state (if it is an AP).•All devices in the system that are capable of delivering interrupts to theprocessors must be inhibited from doing so for the duration of the MP initialization protocol.
The time during which interrupts must be inhibited includes thewindow between when the BSP issues an INIT-SIPI-SIPI sequence to an AP andwhen the AP responds to the last SIPI in the sequence.7.5.3MP Initialization Protocol Algorithm forIntel Xeon ProcessorsFollowing a power-up or RESET of an MP system, the Intel Xeon processors in thesystem execute the MP initialization protocol algorithm to initialize each of the logicalprocessors on the system bus. In the course of executing this algorithm, thefollowing boot-up and initialization operations are carried out:1.
Each logical processor on the system bus is assigned a unique 8-bit APIC ID,based on system topology (see Section 7.5.5, “Identifying Logical Processors inan MP System”). This ID is written into the local APIC ID register for eachprocessor.2. Each logical processor is assigned a unique arbitration priority based on itsAPIC ID.Vol. 3 7-17MULTIPLE-PROCESSOR MANAGEMENT3. Each logical processor executes its internal BIST simultaneously with the otherlogical processors on the system bus.4. Upon completion of the BIST, the logical processors use a hardware-definedselection mechanism to select the BSP and the APs from the available logicalprocessors on the system bus.
The BSP selection mechanism differs dependingon the family, model, and stepping IDs of the processors, as follows:— Family, model, and stepping IDs of F0AH and onwards:•The logical processors begin monitoring the BNR# signal, which istoggling. When the BNR# pin stops toggling, each processor attempts toissue a NOP special cycle on the system bus.•The logical processor with the highest arbitration priority succeeds inissuing a NOP special cycle and is nominated the BSP. This processor setsthe BSP flag in its IA32_APIC_BASE MSR, then fetches and beginsexecuting BIOS boot-strap code, beginning at the reset vector (physicaladdress FFFF FFF0H).•The remaining logical processors (that failed in issuing a NOP specialcycle) are designated as APs.
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