Volume 3A System Programming Guide_ Part 1 (794103), страница 75
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3 7-27MULTIPLE-PROCESSOR MANAGEMENTLogicalProcessor 0ArchitecturalStateLogicalProcessor 1ArchitecturalStateExecution EngineLocal APICLocal APICBus InterfaceSystem BusFigure 7-4. IA-32 Processor with Two Logical Processors Supporting HT Technology7.8.1State of the Logical ProcessorsThe following features are part of the architectural state of logical processors withinIntel 64 or IA-32 processors supporting Hyper-Threading Technology. The featurescan be subdivided into three groups:•••Duplicated for each logical processorShared by logical processors in a physical processorShared or duplicated, depending on the implementationThe following features are duplicated for each logical processor:•••General purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, and EBP)•x87 FPU registers (ST0 through ST7, status word, control word, tag word, dataoperand pointer, and instruction pointer)•••MMX registers (MM0 through MM7)•Debug registers (DR0, DR1, DR2, DR3, DR6, DR7) and the debug control MSRsSegment registers (CS, DS, SS, ES, FS, and GS)EFLAGS and EIP registers.
Note that the CS and EIP/RIP registers for each logicalprocessor point to the instruction stream for the thread being executed by thelogical processor.XMM registers (XMM0 through XMM7) and the MXCSR registerControl registers and system table pointer registers (GDTR, LDTR, IDTR, taskregister)7-28 Vol.
3MULTIPLE-PROCESSOR MANAGEMENT•Machine check global status (IA32_MCG_STATUS) and machine check capability(IA32_MCG_CAP) MSRs•••Thermal clock modulation and ACPI Power management control MSRs••Local APIC registers.Time stamp counter MSRsMost of the other MSR registers, including the page attribute table (PAT). See theexceptions below.Additional general purpose registers (R8-R15), XMM registers (XMM8-XMM15),control register, IA32_EFER on Intel 64 processors.The following features are shared by logical processors:••IA32_MISC_ENABLE MSR (MSR address 1A0H)Memory type range registers (MTRRs)Whether the following features are shared or duplicated is implementation-specific:•Machine check architecture (MCA) MSRs (except for the IA32_MCG_STATUS andIA32_MCG_CAP MSRs)•Performance monitoring control and counter MSRs7.8.2APIC FunctionalityWhen a processor supporting Hyper-Threading Technology support is initialized, eachlogical processor is assigned a local APIC ID (see Table 8-1).
The local APIC ID servesas an ID for the logical processor and is stored in the logical processor’s APIC IDregister. If two or more IA-32 processors supporting Hyper-Threading Technology arepresent in a dual processor (DP) or MP system, each logical processor on the systembus is assigned a unique local APIC ID (see Section 7.10.2, “Identifying LogicalProcessors in an MP System”).Software communicates with local processors using the APIC’s interprocessor interrupt (IPI) messaging facility. Setup and programming for APICs is identical in processors that support and do not support Intel Hyper-Threading Technology. See Chapter8, “Advanced Programmable Interrupt Controller (APIC),” for a detailed discussion.7.8.3Memory Type Range Registers (MTRR)MTRRs in a processor supporting Hyper-Threading Technology are shared by logicalprocessors.
When one logical processor updates the setting of the MTRRs, settingsare automatically shared with the other logical processors in the same physicalpackage.The architectures require that all MP systems based on Intel 64 and IA-32 processors(this includes logical processors) must use an identical MTRR memory map. Thisgives software a consistent view of memory, independent of the processor on whichVol. 3 7-29MULTIPLE-PROCESSOR MANAGEMENTit is running.
See Section 10.11, “Memory Type Range Registers (MTRRs),” for information on setting up MTRRs.7.8.4Page Attribute Table (PAT)Each logical processor has its own PAT MSR (IA32_CR_PAT). However, as describedin Section 10.12, “Page Attribute Table (PAT),” the PAT MSR settings must be thesame for all processors in a system, including the logical processors.7.8.5Machine Check ArchitectureIn the HT Technology context, all of the machine check architecture (MCA) MSRs(except for the IA32_MCG_STATUS and IA32_MCG_CAP MSRs) are duplicated foreach logical processor. This permits logical processors to initialize, configure, query,and handle machine-check exceptions simultaneously within the same physicalprocessor.
The design is compatible with machine check exception handlers thatfollow the guidelines given in Chapter 14, “Machine-Check Architecture.”The IA32_MCG_STATUS MSR is duplicated for each logical processor so that itsmachine check in progress bit field (MCIP) can be used to detect recursion on thepart of MCA handlers. In addition, the MSR allows each logical processor to determine that a machine-check exception is in progress independent of the actions ofanother logical processor in the same physical package.Because the logical processors within a physical package are tightly coupled withrespect to shared hardware resources, both logical processors are notified ofmachine check errors that occur within a given physical processor.
If machine-checkexceptions are enabled when a fatal error is reported, all the logical processors withina physical package are dispatched to the machine-check exception handler. Ifmachine-check exceptions are disabled, the logical processors enter the shutdownstate and assert the IERR# signal.When enabling machine-check exceptions, the MCE flag in control register CR4should be set for each logical processor.7.8.6Debug Registers and ExtensionsEach logical processor has its own set of debug registers (DR0, DR1, DR2, DR3, DR6,DR7) and its own debug control MSR.
These can be set to control and record debuginformation for each logical processor independently. Each logical processor also hasits own last branch records (LBR) stack.7-30 Vol. 3MULTIPLE-PROCESSOR MANAGEMENT7.8.7Performance Monitoring CountersPerformance counters and their companion control MSRs are shared between thelogical processors within the physical processor. As a result, software must managethe use of these resources. The performance counter interrupts, events, and preciseevent monitoring support can be set up and allocated on a per thread (per logicalprocessor) basis.See Section 18.16, “Performance Monitoring and Hyper-Threading Technology,” for adiscussion of performance monitoring in the Intel Xeon processor MP.7.8.8IA32_MISC_ENABLE MSRThe IA32_MISC_ENABLE MSR (MSR address 1A0H) is shared between the logicalprocessors in an IA-32 processor supporting Hyper-Threading Technology.
Thus thearchitectural features that this register controls are set the same for all the logicalprocessors in the same physical package.7.8.9Memory OrderingThe logical processors in an Intel 64 or IA-32 processor supporting Hyper-ThreadingTechnology obey the same rules for memory ordering as Intel 64 or IA-32 processorswithout HT Technology (see Section 7.2, “Memory Ordering”). Each logical processoruses a processor-ordered memory model that can be further defined as “writeordered with store buffer forwarding.” All mechanisms for strengthening or weakening the memory ordering model to handle special programming situations apply toeach logical processor.7.8.10Serializing InstructionsAs a general rule, when a logical processor in a processor supporting HyperThreading Technology executes a serializing instruction, only that logical processor isaffected by the operation.
An exception to this rule is the execution of the WBINVD,INVD, and WRMSR instructions; and the MOV CR instruction when the state of the CDflag in control register CR0 is modified. Here, both logical processors are serialized.7.8.11MICROCODE UPDATE ResourcesIn an Intel processor supporting Hyper-Threading Technology, the microcode updatefacilities are shared between the logical processors; either logical processor caninitiate an update. Each logical processor has its own BIOS signature MSR(IA32_BIOS_SIGN_ID at MSR address 8BH). When a logical processor performs anupdate for the physical processor, the IA32_BIOS_SIGN_ID MSRs for resident logicalprocessors are updated with identical information. If logical processors initiate anVol. 3 7-31MULTIPLE-PROCESSOR MANAGEMENTupdate simultaneously, the processor core provides the necessary synchronizationneeded to insure that only one update is performed at a time.Operating system microcode update drivers that adhere to Intel’s guidelines do notneed to be modified to run on processors supporting Hyper-Threading Technology.7.8.12Self Modifying CodeIntel processors supporting Hyper-Threading Technology support self-modifyingcode, where data writes modify instructions cached or currently in flight.
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