Volume 3A System Programming Guide_ Part 1 (794103), страница 65
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Figure 6-2 shows the format of a TSSfor tasks designed for 32-bit CPUs. The fields of a TSS are divided into two main categories: dynamic fields and static fields.For information about 16-bit Intel 286 processor task structures, see Section 6.6,“16-Bit Task-State Segment (TSS).” For information about 64-bit mode task structures, see Section 6.7, “Task Management in 64-bit Mode.”6-4 Vol. 3TASK MANAGEMENT31015ReservedI/O Map Base AddressLDT Segment SelectorReservedT 10096ReservedGS92ReservedFS88ReservedDS84ReservedSS80ReservedCS76ReservedES72EDI68ESI64EBP60ESP56EBX52EDX48ECX44EAX40EFLAGS36EIP32CR3 (PDBR)28ReservedSS2ReservedSS1SS084ESP0Reserved1612ESP1Reserved2420ESP2Previous Task Link0Reserved bits. Set to 0.Figure 6-2.
32-Bit Task-State Segment (TSS)The processor updates dynamic fields when a task is suspended during a task switch.The following are dynamic fields:•General-purpose register fields — State of the EAX, ECX, EDX, EBX, ESP, EBP,ESI, and EDI registers prior to the task switch.•Segment selector fields — Segment selectors stored in the ES, CS, SS, DS, FS,and GS registers prior to the task switch.•EFLAGS register field — State of the EFAGS register prior to the task switch.Vol.
3 6-5TASK MANAGEMENT•EIP (instruction pointer) field — State of the EIP register prior to the taskswitch.•Previous task link field — Contains the segment selector for the TSS of theprevious task (updated on a task switch that was initiated by a call, interrupt, orexception). This field (which is sometimes called the back link field) permits atask switch back to the previous task by using the IRET instruction.The processor reads the static fields, but does not normally change them.
Thesefields are set up when a task is created. The following are static fields:•LDT segment selector field — Contains the segment selector for the task'sLDT.•CR3 control register field — Contains the base physical address of the pagedirectory to be used by the task. Control register CR3 is also known as the pagedirectory base register (PDBR).•Privilege level-0, -1, and -2 stack pointer fields — These stack pointersconsist of a logical address made up of the segment selector for the stacksegment (SS0, SS1, and SS2) and an offset into the stack (ESP0, ESP1, andESP2).
Note that the values in these fields are static for a particular task;whereas, the SS and ESP values will change if stack switching occurs within thetask.•T (debug trap) flag (byte 100, bit 0) — When set, the T flag causes theprocessor to raise a debug exception when a task switch to this task occurs (seeSection 18.3.1.5, “Task-Switch Exception Condition”).•I/O map base address field — Contains a 16-bit offset from the base of theTSS to the I/O permission bit map and interrupt redirection bitmap. Whenpresent, these maps are stored in the TSS at higher addresses. The I/O map baseaddress points to the beginning of the I/O permission bit map and the end of theinterrupt redirection bit map. See Chapter 13, “Input/Output,” in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 1, for moreinformation about the I/O permission bit map.
See Section 15.3, “Interrupt andException Handling in Virtual-8086 Mode,” for a detailed description of theinterrupt redirection bit map.If paging is used:•Avoid placing a page boundary in the part of the TSS that the processor readsduring a task switch (the first 104 bytes). The processor may not correctlyperform address translations if a boundary occurs in this area. During a taskswitch, the processor reads and writes into the first 104 bytes of each TSS (usingcontiguous physical addresses beginning with the physical address of the firstbyte of the TSS).
So, after TSS access begins, if part of the 104 bytes is notphysically contiguous, the processor will access incorrect information withoutgenerating a page-fault exception.•Pages corresponding to the previous task’s TSS, the current task’s TSS, and thedescriptor table entries for each all should be marked as read/write.6-6 Vol. 3TASK MANAGEMENT•Task switches are carried out faster if the pages containing these structures arepresent in memory before the task switch is initiated.6.2.2TSS DescriptorThe TSS, like all other segments, is defined by a segment descriptor. Figure 6-3shows the format of a TSS descriptor.
TSS descriptors may only be placed in the GDT;they cannot be placed in an LDT or the IDT.An attempt to access a TSS using a segment selector with its TI flag set (which indicates the current LDT) causes a general-protection exception (#GP) to be generatedduring CALLs and JMPs; it causes an invalid TSS exception (#TS) during IRETs. Ageneral-protection exception is also generated if an attempt is made to load asegment selector for a TSS into a segment register.The busy flag (B) in the type field indicates whether the task is busy. A busy task iscurrently running or suspended. A type field with a value of 1001B indicates an inactive task; a value of 1011B indicates a busy task.
Tasks are not recursive. Theprocessor uses the busy flag to detect an attempt to call a task whose execution hasbeen interrupted. To insure that there is only one busy flag is associated with a task,each TSS should have only one TSS descriptor that points to it.TSS Descriptor3124 23 22 21 20 19Base 31:24AG 0 0 VL3116 15 14 13 12 11Limit19:16PDPL08 7Type16 15Base Address 15:00AVLBBASEDPLGLIMITPTYPE4Base 23:160 1 0 B 10Segment Limit 15:000Available for use by system softwareBusy flagSegment Base AddressDescriptor Privilege LevelGranularitySegment LimitSegment PresentSegment TypeFigure 6-3. TSS DescriptorThe base, limit, and DPL fields and the granularity and present flags have functionssimilar to their use in data-segment descriptors (see Section 3.4.5, “SegmentDescriptors”). When the G flag is 0 in a TSS descriptor for a 32-bit TSS, the limit fieldmust have a value equal to or greater than 67H, one byte less than the minimum sizeVol.
3 6-7TASK MANAGEMENTof a TSS. Attempting to switch to a task whose TSS descriptor has a limit less than67H generates an invalid-TSS exception (#TS). A larger limit is required if an I/Opermission bit map is included or if the operating system stores additional data. Theprocessor does not check for a limit greater than 67H on a task switch; however, itdoes check when accessing the I/O permission bit map or interrupt redirection bitmap.Any program or procedure with access to a TSS descriptor (that is, whose CPL isnumerically equal to or less than the DPL of the TSS descriptor) can dispatch the taskwith a call or a jump.In most systems, the DPLs of TSS descriptors are set to values less than 3, so thatonly privileged software can perform task switching. However, in multitasking applications, DPLs for some TSS descriptors may be set to 3 to allow task switching at theapplication (or user) privilege level.6.2.3TSS Descriptor in 64-bit modeIn 64-bit mode, task switching is not supported, but TSS descriptors still exist.
Theformat of a 64-bit TSS is described in Section 6.7.In 64-bit mode, the TSS descriptor is expanded to 16 bytes (see Figure 6-4). Thisexpansion also applies to an LDT descriptor in 64-bit mode. Table 3-2 provides theencoding information for the segment type field.6-8 Vol. 3TASK MANAGEMENTTSS (or LDT) Descriptor3113 12Reserved08 7012Reserved3108Base Address 63:323124 23 22 21 20 19Base 31:24AG 0 0 VL3116 15 14 13 12 11Limit19:16PDPL08 7Type16 15Base Address 15:00AVLBBASEDPLGLIMITPTYPE4Base 23:1600Segment Limit 15:000Available for use by system softwareBusy flagSegment Base AddressDescriptor Privilege LevelGranularitySegment LimitSegment PresentSegment TypeFigure 6-4.
Format of TSS and LDT Descriptors in 64-bit Mode6.2.4Task RegisterThe task register holds the 16-bit segment selector and the entire segmentdescriptor (32-bit base address, 16-bit segment limit, and descriptor attributes) forthe TSS of the current task (see Figure 2-5). This information is copied from the TSSdescriptor in the GDT for the current task.
Figure 6-5 shows the path the processoruses to access the TSS (using the information in the task register).The task register has a visible part (that can be read and changed by software) andan invisible part (maintained by the processor and is inaccessible by software). Thesegment selector in the visible portion points to a TSS descriptor in the GDT. Theprocessor uses the invisible portion of the task register to cache the segmentdescriptor for the TSS.
Caching these values in a register makes execution of the taskmore efficient. The LTR (load task register) and STR (store task register) instructionsload and read the visible portion of the task register:Vol. 3 6-9TASK MANAGEMENTThe LTR instruction loads a segment selector (source operand) into the task registerthat points to a TSS descriptor in the GDT. It then loads the invisible portion of thetask register with information from the TSS descriptor. LTR is a privileged instructionthat may be executed only when the CPL is 0. It’s used during system initialization toput an initial value in the task register.
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