Volume 2B Instruction Set Reference N-Z (794102), страница 10
Текст из файла (страница 10)
2B 4-63INSTRUCTION SET REFERENCE, N-ZPCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 74 /rPCMPEQB mm,mm/m64ValidValidCompare packed bytes inmm/m64 and mm for equality.66 0F 74 /rPCMPEQB xmm1,xmm2/m128ValidValidCompare packed bytes inxmm2/m128 and xmm1 forequality.0F 75 /rPCMPEQW mm,mm/m64ValidValidCompare packed words inmm/m64 and mm for equality.66 0F 75 /rPCMPEQW xmm1,xmm2/m128ValidValidCompare packed words inxmm2/m128 and xmm1 forequality.0F 76 /rPCMPEQD mm,mm/m64ValidValidCompare packed doublewords inmm/m64 and mm for equality.66 0F 76 /rPCMPEQD xmm1,xmm2/m128ValidValidCompare packed doublewords inxmm2/m128 and xmm1 forequality.DescriptionPerforms a SIMD compare for equality of the packed bytes, words, or doublewords inthe destination operand (first operand) and the source operand (second operand).
Ifa pair of data elements is equal, the corresponding data element in the destinationoperand is set to all 1s; otherwise, it is set to all 0s. The source operand can be anMMX technology register or a 64-bit memory location, or it can be an XMM register ora 128-bit memory location. The destination operand can be an MMX technologyregister or an XMM register.The PCMPEQB instruction compares the corresponding bytes in the destination andsource operands; the PCMPEQW instruction compares the corresponding words inthe destination and source operands; and the PCMPEQD instruction compares thecorresponding doublewords in the destination and source operands.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPCMPEQB instruction with 64-bit operands:IF DEST[7:0] = SRC[7:0]THEN DEST[7:0) ← FFH;ELSE DEST[7:0] ← 0; FI;(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)4-64 Vol.
2BPCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, N-ZIF DEST[63:56] = SRC[63:56]THEN DEST[63:56] ← FFH;ELSE DEST[63:56] ← 0; FI;PCMPEQB instruction with 128-bit operands:IF DEST[7:0] = SRC[7:0]THEN DEST[7:0) ← FFH;ELSE DEST[7:0] ← 0; FI;(* Continue comparison of 2nd through 15th bytes in DEST and SRC *)IF DEST[127:120] = SRC[127:120]THEN DEST[127:120] ← FFH;ELSE DEST[127:120] ← 0; FI;PCMPEQW instruction with 64-bit operands:IF DEST[15:0] = SRC[15:0]THEN DEST[15:0] ← FFFFH;ELSE DEST[15:0] ← 0; FI;(* Continue comparison of 2nd and 3rd words in DEST and SRC *)IF DEST[63:48] = SRC[63:48]THEN DEST[63:48] ← FFFFH;ELSE DEST[63:48] ← 0; FI;PCMPEQW instruction with 128-bit operands:IF DEST[15:0] = SRC[15:0]THEN DEST[15:0] ← FFFFH;ELSE DEST[15:0] ← 0; FI;(* Continue comparison of 2nd through 7th words in DEST and SRC *)IF DEST[127:112] = SRC[127:112]THEN DEST[127:112] ← FFFFH;ELSE DEST[127:112] ← 0; FI;PCMPEQD instruction with 64-bit operands:IF DEST[31:0] = SRC[31:0]THEN DEST[31:0] ← FFFFFFFFH;ELSE DEST[31:0] ← 0; FI;IF DEST[63:32] = SRC[63:32]THEN DEST[63:32] ← FFFFFFFFH;ELSE DEST[63:32] ← 0; FI;PCMPEQD instruction with 128-bit operands:IF DEST[31:0] = SRC[31:0]THEN DEST[31:0] ← FFFFFFFFH;ELSE DEST[31:0] ← 0; FI;(* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *)IF DEST[127:96] = SRC[127:96]PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualVol.
2B 4-65INSTRUCTION SET REFERENCE, N-ZTHEN DEST[127:96] ← FFFFFFFFH;ELSE DEST[127:96] ← 0; FI;Intel C/C++ Compiler Intrinsic EquivalentsPCMPEQB __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)PCMPEQW __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)PCMPEQD __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)PCMPEQB __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)PCMPEQW __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)PCMPEQD __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.4-66 Vol. 2BPCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualINSTRUCTION SET REFERENCE, N-Z#UDIf CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for EqualVol.
2B 4-67INSTRUCTION SET REFERENCE, N-ZPCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers forGreater ThanOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 64 /rPCMPGTB mm,mm/m64ValidValidCompare packed signed byteintegers in mm and mm/m64 forgreater than.66 0F 64 /rPCMPGTB xmm1,xmm2/m128ValidValidCompare packed signed byteintegers in xmm1 andxmm2/m128 for greater than.0F 65 /rPCMPGTW mm,mm/m64ValidValidCompare packed signed wordintegers in mm and mm/m64 forgreater than.66 0F 65 /rPCMPGTW xmm1,xmm2/m128ValidValidCompare packed signed wordintegers in xmm1 andxmm2/m128 for greater than.0F 66 /rPCMPGTD mm,mm/m64ValidValidCompare packed signeddoubleword integers in mm andmm/m64 for greater than.66 0F 66 /rPCMPGTD xmm1,xmm2/m128ValidValidCompare packed signeddoubleword integers in xmm1and xmm2/m128 for greaterthan.DescriptionPerforms a SIMD signed compare for the greater value of the packed byte, word, ordoubleword integers in the destination operand (first operand) and the sourceoperand (second operand).
If a data element in the destination operand is greaterthan the corresponding date element in the source operand, the corresponding dataelement in the destination operand is set to all 1s; otherwise, it is set to all 0s. Thesource operand can be an MMX technology register or a 64-bit memory location, or itcan be an XMM register or a 128-bit memory location.
The destination operand canbe an MMX technology register or an XMM register.The PCMPGTB instruction compares the corresponding signed byte integers in thedestination and source operands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source operands; and thePCMPGTD instruction compares the corresponding signed doubleword integers in thedestination and source operands.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).4-68 Vol. 2BPCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater ThanINSTRUCTION SET REFERENCE, N-ZOperationPCMPGTB instruction with 64-bit operands:IF DEST[7:0] > SRC[7:0]THEN DEST[7:0) ← FFH;ELSE DEST[7:0] ← 0; FI;(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)IF DEST[63:56] > SRC[63:56]THEN DEST[63:56] ← FFH;ELSE DEST[63:56] ← 0; FI;PCMPGTB instruction with 128-bit operands:IF DEST[7:0] > SRC[7:0]THEN DEST[7:0) ← FFH;ELSE DEST[7:0] ← 0; FI;(* Continue comparison of 2nd through 15th bytes in DEST and SRC *)IF DEST[127:120] > SRC[127:120]THEN DEST[127:120] ← FFH;ELSE DEST[127:120] ← 0; FI;PCMPGTW instruction with 64-bit operands:IF DEST[15:0] > SRC[15:0]THEN DEST[15:0] ← FFFFH;ELSE DEST[15:0] ← 0; FI;(* Continue comparison of 2nd and 3rd words in DEST and SRC *)IF DEST[63:48] > SRC[63:48]THEN DEST[63:48] ← FFFFH;ELSE DEST[63:48] ← 0; FI;PCMPGTW instruction with 128-bit operands:IF DEST[15:0] > SRC[15:0]THEN DEST[15:0] ← FFFFH;ELSE DEST[15:0] ← 0; FI;(* Continue comparison of 2nd through 7th words in DEST and SRC *)IF DEST[63:48] > SRC[127:112]THEN DEST[127:112] ← FFFFH;ELSE DEST[127:112] ← 0; FI;PCMPGTD instruction with 64-bit operands:IF DEST[31:0] > SRC[31:0]THEN DEST[31:0] ← FFFFFFFFH;ELSE DEST[31:0] ← 0; FI;IF DEST[63:32] > SRC[63:32]THEN DEST[63:32] ← FFFFFFFFH;ELSE DEST[63:32] ← 0; FI;PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater ThanVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
