Volume 2B Instruction Set Reference N-Z (794102), страница 12
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2B 4-77INSTRUCTION SET REFERENCE, N-Z#UDIf CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only). If alignment checking is enabled andunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSSE3[bit 9] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-78 Vol.
2BPHADDW/PHADDD — Packed Horizontal AddINSTRUCTION SET REFERENCE, N-ZPHADDSW — Packed Horizontal Add and SaturateOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 38 03 /rPHADDSW mm1,mm2/m64ValidValidAdd 16-bit signed integershorizontally, pack saturated integersto MM1.ValidValidAdd 16-bit signed integershorizontally, pack saturated integersto XMM1.66 0F 38 03 /r PHADDSW xmm1,xmm2/m128DescriptionPHADDSW adds two adjacent signed 16-bit integers horizontally from the source anddestination operands and saturates the signed results; packs the signed, saturated16-bit results to the destination operand (first operand) Both operands can be MMXor XMM registers. When the source operand is a 128-bit memory operand, theoperand must be aligned on a 16-byte boundary or a general-protection exception(#GP) will be generated.In 64-bit mode, use the REX prefix to access additional registers.OperationPHADDSW with 64-bit operands:mm1[15-0] = SaturateToSignedWord((mm1[31-16] + mm1[15-0]);mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);PHADDSW with 128-bit operands :xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]);xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);xmm1[95-80] = SaturateToSignedWord(xmm2/m128[63-48] + xmm2/m128[47-32]);xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]);Intel C/C++ Compiler Intrinsic EquivalentPHADDSW __m64 _mm_hadds_pi16 (__m64 a, __m64 b)PHADDSW __m128i _mm_hadds_epi16 (__m128i a, __m128i b)PHADDSW — Packed Horizontal Add and SaturateVol.
2B 4-79INSTRUCTION SET REFERENCE, N-ZProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS or GS segments.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.#AC(0):(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made while the current privilegelevel is 3.Real Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#UDIf CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.4-80 Vol.
2BPHADDSW — Packed Horizontal Add and SaturateINSTRUCTION SET REFERENCE, N-Z64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSSE3[bit 9] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PHADDSW — Packed Horizontal Add and SaturateVol.
2B 4-81INSTRUCTION SET REFERENCE, N-ZPHSUBW/PHSUBD — Packed Horizontal Subtract64-BitModeCompat/Leg ModePHSUBW mm1,mm2/m64ValidValidSubtract 16-bit signedintegers horizontally, packto MM1.66 0F 38 05 /rPHSUBW xmm1,xmm2/m128ValidValidSubtract 16-bit signedintegers horizontally, packto XMM1.0F 38 06 /rPHSUBD mm1,mm2/m64ValidValidSubtract 32-bit signedintegers horizontally, packto MM1.66 0F 38 06 /rPHSUBD xmm1,xmm2/m128ValidValidSubtract 32-bit signedintegers horizontally, packto XMM1.OpcodeInstruction0F 38 05 /rDescriptionDescriptionPHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the most significant word from the least significant word of eachpair in the source and destination operands, and packs the signed 16-bit results tothe destination operand (first operand).
PHSUBD performs horizontal subtraction oneach adjacent pair of 32-bit signed integers by subtracting the most significantdoubleword from the least significant doubleword of each pair, and packs the signed32-bit result to the destination operand. Both operands can be MMX or XMM registers. When the source operand is a 128-bit memory operand, the operand must bealigned on a 16-byte boundary or a general-protection exception (#GP) will begenerated.In 64-bit mode, use the REX prefix to access additional registers.OperationPHSUBW with 64-bit operands:mm1[15-0] = mm1[15-0] - mm1[31-16];mm1[31-16] = mm1[47-32] - mm1[63-48];mm1[47-32] = mm2/m64[15-0] - mm2/m64[31-16];mm1[63-48] = mm2/m64[47-32] - mm2/m64[63-48];PHSUBW with 128-bit operands:xmm1[15-0] = xmm1[15-0] - xmm1[31-16];xmm1[31-16] = xmm1[47-32] - xmm1[63-48];xmm1[47-32] = xmm1[79-64] - xmm1[95-80];4-82 Vol. 2BPHSUBW/PHSUBD — Packed Horizontal SubtractINSTRUCTION SET REFERENCE, N-Zxmm1[63-48] = xmm1[111-96] - xmm1[127-112];xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16];xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48];xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80];xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112];PHSUBD with 64-bit operands:mm1[31-0] = mm1[31-0] - mm1[63-32];mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32];PHSUBD with 128-bit operands:xmm1[31-0] = xmm1[31-0] - xmm1[63-32];xmm1[63-32] = xmm1[95-64] - xmm1[127-96];xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32];xmm1[127-96] = xmm2/m128[95-64] - xmm2/m128[127-96];Intel C/C++ Compiler Intrinsic EquivalentsPHSUBW__m64 _mm_hsub_pi16 (__m64 a, __m64 b)PHSUBW__m128i _mm_hsub_epi16 (__m128i a, __m128i b)PHSUBD__m64 _mm_hsub_pi32 (__m64 a, __m64 b)PHSUBD__m128i _mm_hsub_epi32 (__m128i a, __m128i b)Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS or GS segments.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MFIf there is a pending x87 FPU exception (64-bit operations only).#AC(0)(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made while the current privilegelevel is 3.PHSUBW/PHSUBD — Packed Horizontal SubtractVol.
2B 4-83INSTRUCTION SET REFERENCE, N-ZReal Mode Exceptions#GP(0):If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#UD:If CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSSE3[bit 9] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-84 Vol.
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