Volume 2B Instruction Set Reference N-Z (794102), страница 15
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The sourceoperand can be an MMX technology register or a 64-bit memory location, or it can bean XMM register or a 128-bit memory location. The destination operand can be anMMX technology register or an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPMAXUB instruction for 64-bit operands:IF DEST[7:0] > SRC[17:0]) THENDEST[7:0] ← DEST[7:0];ELSEDEST[7:0] ← SRC[7:0]; FI;(* Repeat operation for 2nd through 7th bytes in source and destination operands *)IF DEST[63:56] > SRC[63:56]) THENDEST[63:56] ← DEST[63:56];ELSEDEST[63:56] ← SRC[63:56]; FI;PMAXUB instruction for 128-bit operands:IF DEST[7:0] > SRC[17:0]) THENDEST[7:0] ← DEST[7:0];ELSEDEST[7:0] ← SRC[7:0]; FI;(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF DEST[127:120] > SRC[127:120]) THENDEST[127:120] ← DEST[127:120];PMAXUB—Maximum of Packed Unsigned Byte IntegersVol.
2B 4-101INSTRUCTION SET REFERENCE, N-ZELSEDEST[127:120] ← SRC[127:120]; FI;Intel C/C++ Compiler Intrinsic EquivalentPMAXUB__m64 _mm_max_pu8(__m64 a, __m64 b)PMAXUB__m128i _mm_max_epu8 ( __m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.4-102 Vol.
2BPMAXUB—Maximum of Packed Unsigned Byte IntegersINSTRUCTION SET REFERENCE, N-Z#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PMAXUB—Maximum of Packed Unsigned Byte IntegersVol.
2B 4-103INSTRUCTION SET REFERENCE, N-ZPMINSW—Minimum of Packed Signed Word IntegersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F EA /rPMINSW mm1,mm2/m64ValidValidCompare signed word integers inmm2/m64 and mm1 and returnminimum values.66 0F EA /rPMINSW xmm1,xmm2/m128ValidValidCompare signed word integers inxmm2/m128 and xmm1 and returnminimum values.DescriptionPerforms a SIMD compare of the packed signed word integers in the destinationoperand (first operand) and the source operand (second operand), and returns theminimum value for each pair of word integers to the destination operand. The sourceoperand can be an MMX technology register or a 64-bit memory location, or it can bean XMM register or a 128-bit memory location.
The destination operand can be anMMX technology register or an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPMINSW instruction for 64-bit operands:IF DEST[15:0] < SRC[15:0] THENDEST[15:0] ← DEST[15:0];ELSEDEST[15:0] ← SRC[15:0]; FI;(* Repeat operation for 2nd and 3rd words in source and destination operands *)IF DEST[63:48] < SRC[63:48] THENDEST[63:48] ← DEST[63:48];ELSEDEST[63:48] ← SRC[63:48]; FI;PMINSW instruction for 128-bit operands:IF DEST[15:0] < SRC[15:0] THENDEST[15:0] ← DEST[15:0];ELSEDEST[15:0] ← SRC[15:0]; FI;(* Repeat operation for 2nd through 7th words in source and destination operands *)IF DEST[127:112] < SRC/m64[127:112] THENDEST[127:112] ← DEST[127:112];4-104 Vol.
2BPMINSW—Minimum of Packed Signed Word IntegersINSTRUCTION SET REFERENCE, N-ZELSEDEST[127:112] ← SRC[127:112]; FI;Intel C/C++ Compiler Intrinsic EquivalentPMINSW__m64 _mm_min_pi16 (__m64 a, __m64 b)PMINSW__m128i _mm_min_epi16 ( __m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.PMINSW—Minimum of Packed Signed Word IntegersVol.
2B 4-105INSTRUCTION SET REFERENCE, N-ZIf the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-106 Vol.
2BPMINSW—Minimum of Packed Signed Word IntegersINSTRUCTION SET REFERENCE, N-ZPMINUB—Minimum of Packed Unsigned Byte IntegersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F DA /rPMINUB mm1,mm2/m64ValidValidCompare unsigned byte integers inmm2/m64 and mm1 and returnsminimum values.66 0F DA /rPMINUB xmm1,xmm2/m128ValidValidCompare unsigned byte integers inxmm2/m128 and xmm1 andreturns minimum values.DescriptionPerforms a SIMD compare of the packed unsigned byte integers in the destinationoperand (first operand) and the source operand (second operand), and returns theminimum value for each pair of byte integers to the destination operand.
The sourceoperand can be an MMX technology register or a 64-bit memory location, or it can bean XMM register or a 128-bit memory location. The destination operand can be anMMX technology register or an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPMINUB instruction for 64-bit operands:IF DEST[7:0] < SRC[17:0] THENDEST[7:0] ← DEST[7:0];ELSEDEST[7:0] ← SRC[7:0]; FI;(* Repeat operation for 2nd through 7th bytes in source and destination operands *)IF DEST[63:56] < SRC[63:56] THENDEST[63:56] ← DEST[63:56];ELSEDEST[63:56] ← SRC[63:56]; FI;PMINUB instruction for 128-bit operands:IF DEST[7:0] < SRC[17:0] THENDEST[7:0] ← DEST[7:0];ELSEDEST[7:0] ← SRC[7:0]; FI;(* Repeat operation for 2nd through 15th bytes in source and destination operands *)IF DEST[127:120] < SRC[127:120] THENDEST[127:120] ← DEST[127:120];PMINUB—Minimum of Packed Unsigned Byte IntegersVol.
2B 4-107INSTRUCTION SET REFERENCE, N-ZELSEDEST[127:120] ← SRC[127:120]; FI;Intel C/C++ Compiler Intrinsic EquivalentPMINUB__m64 _m_min_pu8 (__m64 a, __m64 b)PMINUB__m128i _mm_min_epu8 ( __m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.4-108 Vol.
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