Volume 2B Instruction Set Reference N-Z (794102), страница 18
Текст из файла (страница 18)
2BIf a memory operand effective address is outside the SSsegment limit.PMULLW—Multiply Packed Signed Integers and Store Low ResultINSTRUCTION SET REFERENCE, N-Z#UDIf CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0. Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.PMULLW—Multiply Packed Signed Integers and Store Low ResultVol.
2B 4-125INSTRUCTION SET REFERENCE, N-Z#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-126 Vol. 2BPMULLW—Multiply Packed Signed Integers and Store Low ResultINSTRUCTION SET REFERENCE, N-ZPMULUDQ—Multiply Packed Unsigned Doubleword IntegersOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F F4 /rPMULUDQ mm1,mm2/m64ValidValidMultiply unsigned doublewordinteger in mm1 by unsigneddoubleword integer in mm2/m64,and store the quadword result inmm1.66 OF F4 /rPMULUDQ xmm1,xmm2/m128ValidValidMultiply packed unsigneddoubleword integers in xmm1 bypacked unsigned doublewordintegers in xmm2/m128, and storethe quadword results in xmm1.DescriptionMultiplies the first operand (destination operand) by the second operand (sourceoperand) and stores the result in the destination operand.
The source operand can bean unsigned doubleword integer stored in the low doubleword of an MMX technologyregister or a 64-bit memory location, or it can be two packed unsigned doublewordintegers stored in the first (low) and third doublewords of an XMM register or an128-bit memory location. The destination operand can be an unsigned doublewordinteger stored in the low doubleword an MMX technology register or two packeddoubleword integers stored in the first and third doublewords of an XMM register. Theresult is an unsigned quadword integer stored in the destination an MMX technologyregister or two packed unsigned quadword integers stored in an XMM register. Whena quadword result is too large to be represented in 64 bits (overflow), the result iswrapped around and the low 64 bits are written to the destination element (that is,the carry is ignored).For 64-bit memory operands, 64 bits are fetched from memory, but only the lowdoubleword is used in the computation; for 128-bit memory operands, 128 bits arefetched from memory, but only the first and third doublewords are used in thecomputation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPMULUDQ instruction with 64-Bit operands:DEST[63:0] ← DEST[31:0] ∗ SRC[31:0];PMULUDQ instruction with 128-Bit operands:DEST[63:0] ← DEST[31:0] ∗ SRC[31:0];DEST[127:64] ← DEST[95:64] ∗ SRC[95:64];PMULUDQ—Multiply Packed Unsigned Doubleword IntegersVol.
2B 4-127INSTRUCTION SET REFERENCE, N-ZIntel C/C++ Compiler Intrinsic EquivalentPMULUDQ__m64 _mm_mul_su32 (__m64 a, __m64 b)PMULUDQ__m128i _mm_mul_epu32 ( __m128i a, __m128i b)Flags AffectedNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.4-128 Vol.
2BPMULUDQ—Multiply Packed Unsigned Doubleword IntegersINSTRUCTION SET REFERENCE, N-Z#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.PMULUDQ—Multiply Packed Unsigned Doubleword IntegersVol.
2B 4-129INSTRUCTION SET REFERENCE, N-ZPOP—Pop a Value from the StackOpcodeInstruction64-BitModeCompat/Leg ModeDescription8F /0POP r/m16ValidValidPop top of stack into m16; increment stackpointer.8F /0POP r/m32N.E.ValidPop top of stack into m32; increment stackpointer.8F /0POP r/m64ValidN.E.Pop top of stack into m64; increment stackpointer. Cannot encode 32-bit operand size.58+ rwPOP r16ValidValidPop top of stack into r16; increment stackpointer.58+ rdPOP r32N.E.ValidPop top of stack into r32; increment stackpointer.58+ rdPOP r64ValidN.E.Pop top of stack into r64; increment stackpointer. Cannot encode 32-bit operand size.1FPOP DSInvalidValidPop top of stack into DS; increment stackpointer.07POP ESInvalidValidPop top of stack into ES; increment stackpointer.17POP SSInvalidValidPop top of stack into SS; increment stackpointer.0F A1POP FSValidValidPop top of stack into FS; increment stackpointer by 16 bits.0F A1POP FSN.E.ValidPop top of stack into FS; increment stackpointer by 32 bits.0F A1POP FSValidN.E.Pop top of stack into FS; increment stackpointer by 64 bits.0F A9POP GSValidValidPop top of stack into GS; increment stackpointer by 16 bits.0F A9POP GSN.E.ValidPop top of stack into GS; increment stackpointer by 32 bits.0F A9POP GSValidN.E.Pop top of stack into GS; increment stackpointer by 64 bits.DescriptionLoads the value from the top of the stack to the location specified with the destination operand (or explicit opcode) and then increments the stack pointer.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
