Volume 2B Instruction Set Reference N-Z (794102), страница 21
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2B 4-143INSTRUCTION SET REFERENCE, N-Z#UDIf CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0. Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]= 0.
Execution of 128-bit instructions on a non-SSE2 capableprocessor (one that is MMX technology capable) will result in theinstruction operating on the mm registers, not #UD.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)4-144 Vol. 2BIf a memory address referencing the SS segment is in a noncanonical form.POR—Bitwise Logical ORINSTRUCTION SET REFERENCE, N-Z#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.POR—Bitwise Logical ORVol.
2B 4-145INSTRUCTION SET REFERENCE, N-ZPREFETCHh—Prefetch Data Into CachesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F 18 /1PREFETCHT0 m8ValidValidMove data from m8 closer to theprocessor using T0 hint.0F 18 /2PREFETCHT1 m8ValidValidMove data from m8 closer to theprocessor using T1 hint.0F 18 /3PREFETCHT2 m8ValidValidMove data from m8 closer to theprocessor using T2 hint.0F 18 /0PREFETCHNTA m8ValidValidMove data from m8 closer to theprocessor using NTA hint.DescriptionFetches the line of data from memory that contains the byte specified with the sourceoperand to a location in the cache hierarchy specified by a locality hint:•T0 (temporal data)—prefetch data into all levels of the cache hierarchy.— Pentium III processor—1st- or 2nd-level cache.— Pentium 4 and Intel Xeon processors—2nd-level cache.•T1 (temporal data with respect to first level cache)—prefetch data into level 2cache and higher.— Pentium III processor—2nd-level cache.— Pentium 4 and Intel Xeon processors—2nd-level cache.•T2 (temporal data with respect to second level cache)—prefetch data into level 2cache and higher.— Pentium III processor—2nd-level cache.— Pentium 4 and Intel Xeon processors—2nd-level cache.•NTA (non-temporal data with respect to all cache levels)—prefetch data into nontemporal cache structure and into a location close to the processor, minimizingcache pollution.— Pentium III processor—1st-level cache— Pentium 4 and Intel Xeon processors—2nd-level cacheThe source operand is a byte memory location.
(The locality hints are encoded intothe machine level instruction using bits 3 through 5 of the ModR/M byte. Use of anyModR/M value other than the specified ones will lead to unpredictable behavior.)If the line selected is already present in the cache hierarchy at a level closer to theprocessor, no data movement occurs. Prefetches from uncacheable or WC memoryare ignored.4-146 Vol. 2BPREFETCHh—Prefetch Data Into CachesINSTRUCTION SET REFERENCE, N-ZThe PREFETCHh instruction is merely a hint and does not affect program behavior. Ifexecuted, this instruction moves data closer to the processor in anticipation of futureuse.The implementation of prefetch locality hints is implementation-dependent, and canbe overloaded or ignored by a processor implementation.
The amount of dataprefetched is also processor implementation-dependent. It will, however, be aminimum of 32 bytes.It should be noted that processors are free to speculatively fetch and cache data fromsystem memory regions that are assigned a memory-type that permits speculativereads (that is, the WB, WC, and WT memory types). A PREFETCHh instruction isconsidered a hint to this speculative behavior. Because this speculative fetching canoccur at any time and is not tied to instruction execution, a PREFETCHh instruction isnot ordered with respect to the fence instructions (MFENCE, SFENCE, and LFENCE) orlocked memory references.
A PREFETCHh instruction is also unordered with respectto CLFLUSH instructions, other PREFETCHh instructions, or any other general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR,OUT, and MOV CR.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationFETCH (m8);Intel C/C++ Compiler Intrinsic Equivalentvoid _mm_prefetch(char *p, int i)The argument “*p” gives the address of the byte (and corresponding cache line) tobe prefetched. The value “i” gives a constant (_MM_HINT_T0, _MM_HINT_T1,_MM_HINT_T2, or _MM_HINT_NTA) that specifies the type of prefetch operation tobe performed.Numeric ExceptionsNone.Exceptions (All Operating Modes)#UDIf the LOCK prefix is used.PREFETCHh—Prefetch Data Into CachesVol.
2B 4-147INSTRUCTION SET REFERENCE, N-ZPSADBW—Compute Sum of Absolute DifferencesOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F F6 /rPSADBW mm1,mm2/m64ValidValidComputes the absolute differences ofthe packed unsigned byte integersfrom mm2 /m64 and mm1; differencesare then summed to produce anunsigned word integer result.66 0F F6 /rPSADBW xmm1,xmm2/m128ValidValidComputes the absolute differences ofthe packed unsigned byte integersfrom xmm2 /m128 and xmm1; the 8low differences and 8 high differencesare then summed separately toproduce two unsigned word integerresults.DescriptionComputes the absolute value of the difference of 8 unsigned byte integers from thesource operand (second operand) and from the destination operand (first operand).These 8 differences are then summed to produce an unsigned word integer resultthat is stored in the destination operand.
The source operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bitmemory location. The destination operand can be an MMX technology register or anXMM register. Figure 4-5 shows the operation of the PSADBW instruction when using64-bit operands.When operating on 64-bit operands, the word integer result is stored in the low wordof the destination operand, and the remaining bytes in the destination operand arecleared to all 0s.When operating on 128-bit operands, two packed results are computed. Here, the 8low-order bytes of the source and destination operands are operated on to produce aword result that is stored in the low word of the destination operand, and the 8 highorder bytes are operated on to produce a word result that is stored in bits 64 through79 of the destination operand.
The remaining bytes of the destination operand arecleared.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).4-148 Vol. 2BPSADBW—Compute Sum of Absolute DifferencesINSTRUCTION SET REFERENCE, N-ZSRCX7X6X5X4X3X2X1X0DESTY7Y6Y5Y4Y3Y2Y1Y0TEMPABS(X7:Y7) ABS(X6:Y6) ABS(X5:Y5) ABS(X4:Y4) ABS(X3:Y3) ABS(X2:Y2) ABS(X1:Y1) ABS(X0:Y0)DEST00H00H00H00H00H00HSUM(TEMP7...TEMP0)Figure 4-5.
PSADBW Instruction Operation Using 64-bit OperandsOperationPSADBW instructions when using 64-bit operands:TEMP0 ← ABS(DEST[7:0] − SRC[7:0]);(* Repeat operation for bytes 2 through 6 *)TEMP7 ← ABS(DEST[63:56] − SRC[63:56]);DEST[15:0] ← SUM(TEMP0:TEMP7);DEST[63:16] ← 000000000000H;PSADBW instructions when using 128-bit operands:TEMP0 ← ABS(DEST[7:0] − SRC[7:0]);(* Repeat operation for bytes 2 through 14 *)TEMP15 ← ABS(DEST[127:120] − SRC[127:120]);DEST[15:0] ← SUM(TEMP0:TEMP7);DEST[63:16] ← 000000000000H;DEST[79:64] ← SUM(TEMP8:TEMP15);DEST[127:80] ← 000000000000H;Intel C/C++ Compiler Intrinsic EquivalentPSADBW__m64 _mm_sad_pu8(__m64 a,__m64 b)PSADBW__m128i _mm_sad_epu8(__m128i a, __m128i b)Flags AffectedNone.Numeric ExceptionsNone.PSADBW—Compute Sum of Absolute DifferencesVol.
2B 4-149INSTRUCTION SET REFERENCE, N-ZProtected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.4-150 Vol.
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