Volume 2B Instruction Set Reference N-Z (794102), страница 24
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2BPSHUFW—Shuffle Packed WordsINSTRUCTION SET REFERENCE, N-Z#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.PSHUFW—Shuffle Packed WordsVol. 2B 4-167INSTRUCTION SET REFERENCE, N-ZPSIGNB/PSIGNW/PSIGND — Packed SIGN64-BitModeCompat/Leg ModeValidValidNegate packed byte integers in mm1if the corresponding sign in mm2/m64is less than zero.66 0F 38 08 /r PSIGNB xmm1, Validxmm2/m128ValidNegate packed byte integers in xmm1if the corresponding sign inxmm2/m128 is less than zero.0F 38 09 /rValidValidNegate packed 16-bit integers in mm1if the corresponding sign in mm2/m64is less than zero.66 0F 38 09 /r PSIGNW xmm1, Validxmm2/m128ValidNegate packed 16-bit integers inxmm1 if the corresponding sign inxmm2/m128 is less than zero.0F 38 0A /rValidValidNegate packed doubleword integers inmm1 if the corresponding sign inmm2/m64 is less than zero.66 0F 38 0A /r PSIGND xmm1, Validxmm2/m128ValidNegate packed doubleword integers inxmm1 if the corresponding sign inxmm2/m128 is less than zero.OpcodeInstruction0F 38 08 /rPSIGNB mm1,mm2/m64PSIGNW mm1,mm2/m64PSIGND mm1,mm2/m64DescriptionDescriptionPSIGNB/PSIGNW/PSIGND negates each data element of the destination operand(the first operand) if the sign of the corresponding data element in the sourceoperand (the second operand) is less than zero.
If the sign of a data element in thesource operand is positive, the corresponding data element in the destinationoperand is unchanged. If a data element in the source operand is zero, the corresponding data element in the destination operand is set to zero.PSIGNB operates on signed bytes. PSIGNW operates on 16-bit signed words.PSIGND operates on signed 32-bit integers. Both operands can be MMX register orXMM registers. When the source operand is a 128bit memory operand, the operandmust be aligned on a 16-byte boundary or a general-protection exception (#GP) willbe generated.In 64-bit mode, use the REX prefix to access additional registers.OperationPSIGNB with 64 bit operands:IF (SRC[7:0] < 0 )DEST[7:0] ← Neg(DEST[7:0])4-168 Vol.
2BPSIGNB/PSIGNW/PSIGND — Packed SIGNINSTRUCTION SET REFERENCE, N-ZELSEIF (SRC[7:0] == 0 )DEST[7:0] ← 0ELSEIF (SRC[7:0] > 0 )DEST[7:0] ← DEST[7:0]Repeat operation for 2nd through 7th bytesIF (SRC[63:56] < 0 )DEST[63:56] ← Neg(DEST[63:56])ELSEIF (SRC[63:56] == 0 )DEST[63:56] ← 0ELSEIF (SRC[63:56] > 0 )DEST[63:56] ← DEST[63:56]PSIGNB with 128 bit operands:IF (SRC[7:0] < 0 )DEST[7:0] ← Neg(DEST[7:0])ELSEIF (SRC[7:0] == 0 )DEST[7:0] ← 0ELSEIF (SRC[7:0] > 0 )DEST[7:0] ← DEST[7:0]Repeat operation for 2nd through 15th bytesIF (SRC[127:120] < 0 )DEST[127:120] ← Neg(DEST[127:120])ELSEIF (SRC[127:120] == 0 )DEST[127:120] ← 0ELSEIF (SRC[127:120] > 0 )DEST[127:120] ← DEST[127:120]PSIGNW with 64 bit operands:IF (SRC[15:0] < 0 )DEST[15:0] ← Neg(DEST[15:0])ELSEIF (SRC[15:0] == 0 )DEST[15:0] ← 0ELSEIF (SRC[15:0] > 0 )DEST[15:0] ← DEST[15:0]Repeat operation for 2nd through 3rd wordsIF (SRC[63:48] < 0 )DEST[63:48] ← Neg(DEST[63:48])ELSEIF (SRC[63:48] == 0 )DEST[63:48] ← 0ELSEIF (SRC[63:48] > 0 )DEST[63:48] ← DEST[63:48]PSIGNB/PSIGNW/PSIGND — Packed SIGNVol.
2B 4-169INSTRUCTION SET REFERENCE, N-ZPSIGNW with 128 bit operands:IF (SRC[15:0] < 0 )DEST[15:0] ← Neg(DEST[15:0])ELSEIF (SRC[15:0] == 0 )DEST[15:0] ← 0ELSEIF (SRC[15:0] > 0 )DEST[15:0] ← DEST[15:0]Repeat operation for 2nd through 7th wordsIF (SRC[127:112] < 0 )DEST[127:112] ← Neg(DEST[127:112])ELSEIF (SRC[127:112] == 0 )DEST[127:112] ← 0ELSEIF (SRC[127:112] > 0 )DEST[127:112] ← DEST[127:112]PSIGND with 64 bit operands:IF (SRC[31:0] < 0 )DEST[31:0] ← Neg(DEST[31:0])ELSEIF (SRC[31:0] == 0 )DEST[31:0] ← 0ELSEIF (SRC[31:0] > 0 )DEST[31:0] ← DEST[31:0]IF (SRC[63:32] < 0 )DEST[63:32] ← Neg(DEST[63:32])ELSEIF (SRC[63:32] == 0 )DEST[63:32] ← 0ELSEIF (SRC[63:32] > 0 )DEST[63:32] ← DEST[63:32]PSIGND with 128 bit operands:IF (SRC[31:0] < 0 )DEST[31:0] ← Neg(DEST[31:0])ELSEIF (SRC[31:0] == 0 )DEST[31:0] ← 0ELSEIF (SRC[31:0] > 0 )DEST[31:0] ← DEST[31:0]Repeat operation for 2nd through 3rd double wordsIF (SRC[127:96] < 0 )DEST[127:96] ← Neg(DEST[127:96])ELSEIF (SRC[127:96] == 0 )DEST[127:96] ← 0ELSEIF (SRC[127:96] > 0 )4-170 Vol.
2BPSIGNB/PSIGNW/PSIGND — Packed SIGNINSTRUCTION SET REFERENCE, N-ZDEST[127:96] ← DEST[127:96]Intel C/C++ Compiler Intrinsic EquivalentPSIGNB__m64 _mm_sign_pi8 (__m64 a, __m64 b)PSIGNB__m128i _mm_sign_epi8 (__m128i a, __m128i b)PSIGNW__m64 _mm_sign_pi16 (__m64 a, __m64 b)PSIGNW__m128i _mm_sign_epi16 (__m128i a, __m128i b)PSIGND__m64 _mm_sign_pi32 (__m64 a, __m64 b)PSIGND__m128i _mm_sign_epi32 (__m128i a, __m128i b)Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS or GS segments.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#UDIf CR0.EM = 1.(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.#AC(0)(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made while the current privilegelevel is 3.Real Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.(128-bit operations only) If not aligned on 16-byte boundary,regardless of segment.#UD(128-bit operations only) If CR0.EM = 1.If CR4.OSFXSR(bit 9) = 0.If CPUID.SSSE3(ECX bit 9) = 0.If the LOCK prefix is used.#NMIf TS bit in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.PSIGNB/PSIGNW/PSIGND — Packed SIGNVol.
2B 4-171INSTRUCTION SET REFERENCE, N-ZVirtual 8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled andunaligned memory reference is made.Compatibility Mode ExceptionsSame as for protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSSE3[bit 9] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-172 Vol.
2BPSIGNB/PSIGNW/PSIGND — Packed SIGNINSTRUCTION SET REFERENCE, N-ZPSLLDQ—Shift Double Quadword Left LogicalOpcodeInstruction64-BitModeCompat/Leg ModeDescription66 0F 73 /7 ibPSLLDQ xmm1,imm8ValidValidShift xmm1 left by imm8 byteswhile shifting in 0s.DescriptionShifts the destination operand (first operand) to the left by the number of bytes specified in the count operand (second operand).
The empty low-order bytes are cleared(set to all 0s). If the value specified by the count operand is greater than 15, thedestination operand is set to all 0s. The destination operand is an XMM register. Thecount operand is an 8-bit immediate.OperationTEMP ← COUNT;IF (TEMP > 15) THEN TEMP ← 16; FI;DEST ← DEST << (TEMP ∗ 8);Intel C/C++ Compiler Intrinsic EquivalentPSLLDQ__m128i _mm_slli_si128 ( __m128i a, int imm)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.Real-Address Mode ExceptionsSame exceptions as in protected mode.PSLLDQ—Shift Double Quadword Left LogicalVol.
2B 4-173INSTRUCTION SET REFERENCE, N-ZVirtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.4-174 Vol. 2BPSLLDQ—Shift Double Quadword Left LogicalINSTRUCTION SET REFERENCE, N-ZPSLLW/PSLLD/PSLLQ—Shift Packed Data Left LogicalOpcodeInstruction0F F1 /r64-BitModeCompat/Leg ModeDescriptionPSLLW mm, mm/m64 ValidValidShift words in mm left mm/m64while shifting in 0s.66 0F F1 /rPSLLW xmm1,xmm2/m128ValidValidShift words in xmm1 left byxmm2/m128 while shifting in 0s.0F 71 /6 ibPSLLW xmm1, imm8ValidValidShift words in mm left by imm8while shifting in 0s.66 0F 71 /6 ibPSLLW xmm1, imm8ValidValidShift words in xmm1 left byimm8 while shifting in 0s.0F F2 /rPSLLD mm, mm/m64ValidValidShift doublewords in mm left bymm/m64 while shifting in 0s.66 0F F2 /rPSLLD xmm1,xmm2/m128ValidValidShift doublewords in xmm1 leftby xmm2/m128 while shifting in0s.0F 72 /6 ibPSLLD mm, imm8ValidValidShift doublewords in mm left byimm8 while shifting in 0s.66 0F 72 /6 ibPSLLD xmm1, imm8ValidValidShift doublewords in xmm1 leftby imm8 while shifting in 0s.0F F3 /rPSLLQ mm, mm/m64ValidValidShift quadword in mm left bymm/m64 while shifting in 0s.66 0F F3 /rPSLLQ xmm1,xmm2/m128ValidValidShift quadwords in xmm1 left byxmm2/m128 while shifting in 0s.0F 73 /6 ibPSLLQ mm, imm8ValidValidShift quadword in mm left byimm8 while shifting in 0s.66 0F 73 /6 ibPSLLQ xmm1, imm8ValidValidShift quadwords in xmm1 left byimm8 while shifting in 0s.DescriptionShifts the bits in the individual data elements (words, doublewords, or quadword) inthe destination operand (first operand) to the left by the number of bits specified inthe count operand (second operand).
As the bits in the data elements are shifted left,the empty low-order bits are cleared (set to 0). If the value specified by the countoperand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand is set to all 0s.
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