Volume 2B Instruction Set Reference N-Z (794102), страница 28
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2BPSUBQ—Subtract Packed Quadword IntegersINSTRUCTION SET REFERENCE, N-ZFlags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.PSUBQ—Subtract Packed Quadword IntegersVol.
2B 4-197INSTRUCTION SET REFERENCE, N-Z#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-198 Vol.
2BPSUBQ—Subtract Packed Quadword IntegersINSTRUCTION SET REFERENCE, N-ZPSUBSB/PSUBSW—Subtract Packed Signed Integers with SignedSaturationOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F E8 /rPSUBSB mm,mm/m64ValidValidSubtract signed packed bytes inmm/m64 from signed packed bytesin mm and saturate results.66 0F E8 /rPSUBSB xmm1,xmm2/m128ValidValidSubtract packed signed byteintegers in xmm2/m128 frompacked signed byte integers inxmm1 and saturate results.0F E9 /rPSUBSW mm,mm/m64ValidValidSubtract signed packed words inmm/m64 from signed packed wordsin mm and saturate results.66 0F E9 /rPSUBSW xmm1,xmm2/m128ValidValidSubtract packed signed wordintegers in xmm2/m128 frompacked signed word integers inxmm1 and saturate results.DescriptionPerforms a SIMD subtract of the packed signed integers of the source operand(second operand) from the packed signed integers of the destination operand (firstoperand), and stores the packed integer results in the destination operand.
SeeFigure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 1, for an illustration of a SIMD operation. Overflow is handled with signedsaturation, as described in the following paragraphs.These instructions can operate on either 64-bit or 128-bit operands. When operatingon 64-bit operands, the destination operand must be an MMX technology registerand the source operand can be either an MMX technology register or a 64-bitmemory location. When operating on 128-bit operands, the destination operandmust be an XMM register and the source operand can be either an XMM register or a128-bit memory location.The PSUBSB instruction subtracts packed signed byte integers.
When an individualbyte result is beyond the range of a signed byte integer (that is, greater than 7FH orless than 80H), the saturated value of 7FH or 80H, respectively, is written to thedestination operand.The PSUBSW instruction subtracts packed signed word integers. When an individualword result is beyond the range of a signed word integer (that is, greater than 7FFFHor less than 8000H), the saturated value of 7FFFH or 8000H, respectively, is writtento the destination operand.PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed SaturationVol.
2B 4-199INSTRUCTION SET REFERENCE, N-ZIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationPSUBSB instruction with 64-bit operands:DEST[7:0] ← SaturateToSignedByte (DEST[7:0] − SRC (7:0]);(* Repeat subtract operation for 2nd through 7th bytes *)DEST[63:56] ← SaturateToSignedByte (DEST[63:56] − SRC[63:56] );PSUBSB instruction with 128-bit operands:DEST[7:0] ← SaturateToSignedByte (DEST[7:0] − SRC[7:0]);(* Repeat subtract operation for 2nd through 14th bytes *)DEST[127:120] ← SaturateToSignedByte (DEST[111:120] − SRC[127:120]);PSUBSW instruction with 64-bit operandsDEST[15:0] ← SaturateToSignedWord (DEST[15:0] − SRC[15:0] );(* Repeat subtract operation for 2nd and 7th words *)DEST[63:48] ← SaturateToSignedWord (DEST[63:48] − SRC[63:48] );PSUBSW instruction with 128-bit operandsDEST[15:0] ← SaturateToSignedWord (DEST[15:0] − SRC[15:0]);(* Repeat subtract operation for 2nd through 7th words *)DEST[127:112] ← SaturateToSignedWord (DEST[127:112] − SRC[127:112]);Intel C/C++ Compiler Intrinsic EquivalentsPSUBSB__m64 _mm_subs_pi8(__m64 m1, __m64 m2)PSUBSB__m128i _mm_subs_epi8(__m128i m1, __m128i m2)PSUBSW__m64 _mm_subs_pi16(__m64 m1, __m64 m2)PSUBSW__m128i _mm_subs_epi16(__m128i m1, __m128i m2)Flags AffectedNone.Numeric ExceptionsNone.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.4-200 Vol.
2BPSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed SaturationINSTRUCTION SET REFERENCE, N-Z#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.Real-Address Mode Exceptions#GP(0)(128-bit operations only) If a memory operand is not aligned ona 16-byte boundary, regardless of segment.If any part of the operand lies outside of the effective addressspace from 0 to FFFFH.#UDIf CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.(128-bit operations only) If memory operand is not aligned on a16-byte boundary, regardless of segment.PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed SaturationVol.
2B 4-201INSTRUCTION SET REFERENCE, N-Z#SS(0)#UDIf a memory operand effective address is outside the SSsegment limit.If CR0.EM[bit 2] = 1.(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#NMIf CR0.TS[bit 3] = 1.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)(64-bit operations only) If alignment checking is enabled and anunaligned memory reference is made while the current privilegelevel is 3.4-202 Vol. 2BPSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed SaturationINSTRUCTION SET REFERENCE, N-ZPSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers withUnsigned SaturationOpcodeInstruction64-BitModeCompat/Leg ModeDescription0F D8 /rPSUBUSB mm,mm/m64ValidValidSubtract unsigned packed bytes inmm/m64 from unsigned packedbytes in mm and saturate result.66 0F D8 /rPSUBUSB xmm1,xmm2/m128ValidValidSubtract packed unsigned byteintegers in xmm2/m128 from packedunsigned byte integers in xmm1 andsaturate result.0F D9 /rPSUBUSW mm,mm/m64ValidValidSubtract unsigned packed words inmm/m64 from unsigned packedwords in mm and saturate result.66 0F D9 /rPSUBUSW xmm1,xmm2/m128ValidValidSubtract packed unsigned wordintegers in xmm2/m128 from packedunsigned word integers in xmm1 andsaturate result.DescriptionPerforms a SIMD subtract of the packed unsigned integers of the source operand(second operand) from the packed unsigned integers of the destination operand (firstoperand), and stores the packed unsigned integer results in the destination operand.See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled withunsigned saturation, as described in the following paragraphs.These instructions can operate on either 64-bit or 128-bit operands. When operatingon 64-bit operands, the destination operand must be an MMX technology registerand the source operand can be either an MMX technology register or a 64-bitmemory location. When operating on 128-bit operands, the destination operandmust be an XMM register and the source operand can be either an XMM register or a128-bit memory location.The PSUBUSB instruction subtracts packed unsigned byte integers. When an individual byte result is less than zero, the saturated value of 00H is written to the destination operand.The PSUBUSW instruction subtracts packed unsigned word integers.
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